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PRELIMINARY DATA SHEET
SDA 9415-B13 DAEDALUS
Display Processor and Scan Rate Converter using Embedded DRAM Technology Units
Edition Feb. 28, 2001 6251-560-1PD
SDA 9415 - B13 Revision History: Previous Versions:
2000-05 (V 1.0) 1999-04-01
Changes to the previous issue Version 00, Edition 04.99, are marked with a change bar 05.2000 editorial changes only (no change of content)
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Preliminary Data Sheet
1 2 3 4 5 5.1 5.2 5.3 5.4 5.4.1 5.4.2 5.4.2.1 5.4.2.2 5.4.3 5.4.3.1 5.4.3.2 5.4.4 5.4.5 5.5 5.6 5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 5.6.6 5.6.7 5.6.8 5.6.9 5.7 5.7.1 5.7.2 5.7.3 5.7.4 5.8 5.9 5.10 5.11 5.12 5.12.1
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Pin Diagram: P-MQFP-144-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 System description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Input sync controller (ISCM/ISCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Input format conversion (IFCM/IFCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Input signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Adjustable delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Vertical and horizontal compression (VHCOMM/VHCOMS) . . . . . . . . . .36 Vertical compression and peaking . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Horizontal compression/expansion and panorama mode . . . . . . . . . .40 Noise reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Spatial noise reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Motion adaptive temporal noise reduction . . . . . . . . . . . . . . . . . . . . . .45 Noise measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Letter box detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Clock concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Application modes and memory concept . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Configuration controlling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 SRC mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 SSC and MUP mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Configuration switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Joint line free display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Master slave switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Refresh and still picture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Memory management and animation controlling . . . . . . . . . . . . . . . . . . .74 Output sync controller (OSCM/S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 HOUT generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 VOUT generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Switching from H-and-V-freerunning to H-and-V-locked mode . . . . . . . .87 Operation mode generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Motion estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Motion compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Global motion, film mode and phase detection . . . . . . . . . . . . . . . . . . . . .108 Vertical expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 Display processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 Peaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
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5.12.2 5.12.3 5.12.4 5.12.5 5.12.6 5.12.7 5.13 5.13.1 5.13.2 5.13.3 5.13.4 6 6.1 6.2 6.3 7 8 8.1 8.2 8.3 8.4 9
Digital luminance transition improvement . . . . . . . . . . . . . . . . . . . . . . .115 Digital colour transition improvement . . . . . . . . . . . . . . . . . . . . . . . . . .117 Output format conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 Insertion facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 Coarse delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 Digital-to-Analog conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 IC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 IC Bus slave address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 IC Bus format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 IC Bus commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 Detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 Characteristics (Under operating range conditions) . . . . . . . . . . . . . . . . .179 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 Wave forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 IC Bus timing START/STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 IC Bus timing DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 Timing diagram clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 Clock circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
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Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43
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Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Block diagram 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Principles of SRC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Principles of SSC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Principles of MUP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Input IC Bus parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Field detection and VINM delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Explanation of 656 format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 SYNCENM/SYNCENS signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Block diagram of input processing blocks . . . . . . . . . . . . . . . . . . . . . . .34 Block diagram of VHCOMM/VHCOMS . . . . . . . . . . . . . . . . . . . . . . . . .36 Principles of panorama mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Block diagram of noise reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Block diagram of motion detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 LUT for motion detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Example of noise measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Principle of letter box detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Block diagram of letter box detection . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Histogram and line type decision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Visibility of letter box detection IC Bus parameters . . . . . . . . . . . . . . .53 Clock concept of SDA 9415 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Application for SDA 9415 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Supported data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Switching from SRC-PIP mode to SSC mode . . . . . . . . . . . . . . . . . . . .67 Changing picture sizes to get a double window display. . . . . . . . . . . . .68 Completing the operations to a master slave exchange . . . . . . . . . . . .69 Example for animation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Equation of the position of the left upper picture corner . . . . . . . . . . . .75 Explanation of memory management I . . . . . . . . . . . . . . . . . . . . . . . . .76 Explanation of memory management II . . . . . . . . . . . . . . . . . . . . . . . . .77 Explanation of memory management III . . . . . . . . . . . . . . . . . . . . . . . .78 Block diagram of OSCM/S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Output IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Output write IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Ingenious configurations of the HOUT and VOUT generator . . . . . . . .84 VOUT generation depending on IC Bus parameter RMODE . . . . . . . .86 Explanation of field and display line-scanning pattern . . . . . . . . . . . . . .88 Explanation of operation mode timing . . . . . . . . . . . . . . . . . . . . . . . . . .89 Principle of block matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Block diagram of motion estimation and compensation. . . . . . . . . . . .101 Block diagram of motion estimation . . . . . . . . . . . . . . . . . . . . . . . . . . .102
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Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55
Relative positions of the spatial predictors . . . . . . . . . . . . . . . . . . . . .102 Timing of 100 Hz scan rate conversion . . . . . . . . . . . . . . . . . . . . . . . .104 Principles of motion compensation . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Principles of motion compensation for the b field (FILSEL=0). . . . . . .105 Output sequence generation: Camera mode. . . . . . . . . . . . . . . . . . . .106 Output sequence generation: PAL film mode . . . . . . . . . . . . . . . . . . .107 Output sequence generation: NTSC film mode . . . . . . . . . . . . . . . . . .107 Calculation of maximum VPAN value . . . . . . . . . . . . . . . . . . . . . . . . .112 Block diagram of display processing . . . . . . . . . . . . . . . . . . . . . . . . . .113 Block diagram peaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 Principles of DCTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 Application for SDA 9415. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
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Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43
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Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input write IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input write IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input write IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input read IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input sync formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELM/DELS IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Examples of vertical filter adjustment . . . . . . . . . . . . . . . . . . . . . . . . . Conversion table between dezV and DEZVM / DEZVS. . . . . . . . . . . . Input write IC Bus parameter YPEAKM/YPEAKS/CPEAKM/CPEAKS Input write IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Examples of horizontal filter adjustment . . . . . . . . . . . . . . . . . . . . . . . Conversion table between dezH and DEZHM/DEZMS . . . . . . . . . . . . Input write IC Bus parameter CHFILM/CHFILS . . . . . . . . . . . . . . . . . Filter IC Bus parameter in case of PANAON=1 . . . . . . . . . . . . . . . . . IC Bus parameter PANAST in case of PANAON=1 . . . . . . . . . . . . . . Input write IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input write IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC Bus parameter TNRVAY/C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC Bus parameter TNRHOY/C and TNRKOY/C . . . . . . . . . . . . . . . . . IC Bus parameter TNRCLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input write IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input write IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input read IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Line Type Decision of LBD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Evaluation of the reliability signal RELY . . . . . . . . . . . . . . . . . . . . . . . Correction of "start/end-line decision filter" block . . . . . . . . . . . . . . . . . Input write IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input read IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock concept switching matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input write IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Definition of MEMOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Definition of CHRFORM/CHRFORS . . . . . . . . . . . . . . . . . . . . . . . . . . Definition of ORGMEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Definition of ORGMEMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Definition of VERRESM/VERRESS . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable data configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications of different data configurations . . . . . . . . . . . . . . . . . . . .
19 26 27 28 29 29 30 30 31 35 38 38 39 39 41 41 42 42 43 43 44 47 47 47 48 49 50 51 52 53 54 54 55 55 56 57 58 58 59 59 60 61 62
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Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 Table 69 Table 70 Table 71 Table 72 Table 73 Table 74 Table 75 Table 76 Table 77 Table 78 Table 79 Table 80 Table 81 Table 82 Table 83 Table 84 Table 85 Table 86
10
Maximum picture sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Definition of MEMWRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Definition of MEMWRM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Input write IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Definition of WRFLDM/WRFLDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Input write IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Definition of ORGMEMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Definition of ORGMEMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Definition of MEMRDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Definition of MEMRDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Definition of MEMWRM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Definition of MEMWRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Switching from SRC PIP mode to SSC mode . . . . . . . . . . . . . . . . . . . 68 Changing the picture sizes to double window format. . . . . . . . . . . . . . 69 Performing a master slave exchange . . . . . . . . . . . . . . . . . . . . . . . . . 70 Input write IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Output read IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Supported data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Input write IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Output read IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Input write IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Input write IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Input write IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Output write IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Output write IC Bus parameter INTMODE . . . . . . . . . . . . . . . . . . . . . 86 Output write IC Bus parameter INTMODE . . . . . . . . . . . . . . . . . . . . . 86 Static operation modes (only valid for ADOPMOM=0, RMODE=0) . . . 90 Static operation modes (only valid for ADOPMOM=0, RMODE=1) . . . 91 Special combinations of STOPMOM and ADOPMOM . . . . . . . . . . . . 92 Display line-scanning pattern sequence . . . . . . . . . . . . . . . . . . . . . . . 93 Static operation modes slave. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Adaptive operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Output write IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Key IC Bus parameters of the 3-D RS motion estimation. . . . . . . . . 100 Output write IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Output write IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Principles of global motion and film mode detection . . . . . . . . . . . . . 109 Definition of scmin/scmax depending on SFMINTH/SFMAXTH . . . . 109 Output write IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Output read IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Output write IC Bus parameter VERINT . . . . . . . . . . . . . . . . . . . . . . 111 Examples of reachable expansion factors . . . . . . . . . . . . . . . . . . . . . 112
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Table 87 Table 88 Table 89 Table 90 Table 91 Table 92 Table 93 Table 94 Table 95 Table 96 Table 97 Table 98 Table 99 Table 100 Table 101 Table 102
Output write IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conversion table BCOF/HCOF to gain_bp/gain_hp . . . . . . . . . . . . . Output write IC Bus parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC Bus parameter THRESY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC Bus parameter THRESY_UP . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC Bus parameter ASCENTLTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output write IC Bus parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC Bus parameter THRESC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC Bus parameter ASCENTCTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output write IC Bus parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output write parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output write parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output write IC Bus parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output write IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output write IC Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
113 113 115 115 116 116 117 117 118 119 119 120 121 121 122 122
11
Micronas
SDA 9415 - B13
Preliminary Data Sheet
12
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Introduction
1
Introduction
(R)
The SDA 9415 is a new component of the Micronas MEGAVISION IC set, which enables the system to reduce large area and line flickering of interlaced TV standards. The scan rate conversion to 100/120 Hz interlaced or 50/60 Hz progressive scan is motion vector based. For the 100/120 Hz (50/60 Hz) conversion the SDA 9415 really calculates 100/120 Hz (50/60 Hz) fields with continuous motion phases to avoid double contour effects in the motion display. In the special case of movie sources, which have a non-continuous motion phase, the SDA 9415 generates at the output an appropriate sequence with a continuous motion phase (True Motion"). Due to the frame based signal processing, the noise reduction has been greatly improved. Furthermore different motion detectors for luminance and chrominance have been implemented. For automatic controlling of the noise reduction parameters a noise measurement algorithm is included, which measures the noise level in the picture or in the blanking period. In addition a spatial noise reduction is implemented, which reduces the noise even in the case of motion. The SDA 9415 has two input channels, which can be used for different features like Picture-in-Picture (maximum approximately 1/9 picture) and "Double-window/Splitscreen". The two input signals can be scaled horizontally and vertically with variable factors. Panorama modes will be supported. Besides that an algorithm for the detection of letter box pictures is included. The SDA 9415 delivers the start and the end line of the active picture part of the input signal to an external C. The C calculates the zoom factors for displaying the active picture part on the full screen and sends this values back to the SDA 9415. Picture sharpness can be greatly improved by a LTI (luminance transition improvement) or/and peaking and a CTI (colour transition improvement) algorithm. The resolution of the output signals is 9 bit. The SDA 9415 has analog output signals.
13
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Features
2
Features
* Different application modes - SRC mode: - High performance scan rate converter - High performance scan rate converter plus high resolution frame based joint-linefree Picture-in-Picture (maximum approximately 1/9 picture) - SSC mode: - Split screen applications with two signal sources (e.g. double window) - MUP mode: - Multipicture display mode (e.g. tuner scan) * 8 bit amplitude resolution of each input channel - Two input channels - Input frequency up to 27 MHz - ITU-R 656 data format (8 wires data only and additional sync information or 8 wires including sync information) - 4:2:2 luminance and chrominance parallel (2x8 wires) * Two different representations of input chrominance data - 2's complement code - Positive dual code * Two flexible input sync controllers * Vertical peaking of the input signal * Flexible scaling of the input signal - Flexible digital vertical compression of the input signal (1.0, ... [2 line resolution] ... , 1/32) - Flexible horizontal compression and expansion of the input signal (2.0, ... [4 pixel resolution] ... ,1.0 , ... [4 pixel resolution] ... , 1/32) - Panorama mode (programmable characteristic) * Noise reduction - Motion adaptive spatial and temporal noise reduction (3D-NR) - Temporal noise reduction for luminance and chrominance, frame based or field based - Different motion detectors for luminance and chrominance or identical - Flexible programming of the temporal noise reduction parameters - Automatic measurement of the noise level (5 bit value, readable by IC-bus) * 3-D motion estimation - High performance motion estimation based on block matching algorithm - Film mode detector (PAL and NTSC), Global motion flag (readable by IC bus) * Automatic detection of letter box formats (readable by IC bus) * TV mode detection by counting line numbers (PAL, NTSC, readable by IC bus) * Embedded memory - 6 Mbit embedded DRAM core for field memories - 1,1 Mbit embedded DRAM core for line memories, vector memory, block-to-line
14 Micronas
SDA 9415 - B13
Preliminary Data Sheet
Features converter - 36 kbit SRAM for block matching, line-to-block converter Flexible clock and synchronization concept - Decoupling of the input and output clock system possible Scan rate conversion - Motion compensated 100/120 Hz interlaced scan conversion (Micronas VDU) - Motion compensated 50/60 Hz progressive scan conversion (Micronas VDU) - Simple interlaced modes: ABAB, AABB, AAAA, BBBB - Simple progressive modes: AB, AA*, B*B - True Motion: 50 Hz motion resolution even for 25 Hz PAL film sources 60 Hz motion resolution even for 30 Hz NTSC film sources - Large area and line flicker reduction Flexible digital vertical expansion of the output signal (1.0, ... [1/64] ... , 2.0) Sharpness improvement - Digital colour transition improvement (DCTI) - Digital luminance transition improvement (DLTI) - Peaking (luminance only) Flexible output sync controller - Flexible positioning of the two output channels in all application modes - Flexible height and width of the two output pictures - Flexible programming of the output sync raster Signal manipulations - Still frame or field - Insertion of coloured background - Insertion of a selection border - Adjustable delay between Y and UV signal (+4,...[1]...,-3 input pixels) at the input side - Adjustable delay between Y and UV signal (+3,...[0.5]...,- 4 output pixels) at the output side Three D/A converters - 9 bit amplitude resolution for Y, -(R-Y), -(B-Y) output - 60 MHz maximal clock frequency - Two-fold oversampling - Simplification of external analog post filtering and differential analog outputs IC-bus control (400 kHz) P-MQFP-100 package 3.3 V 5% supply voltage
* *
* *
*
*
*
* * *
15
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Block diagram
3
Block diagram
TEST RESET X2 X1/CLKD
HINM VINM SYNCENM
ISCM Input sync controller Master
LBD Letter box detection
LM Line memory
VM Vector memory
ME motion estimation
clock doubling PLLD
CLKOUT OSCM/S Output sync controller Master INTERLACED HOUT VOUT BLANK
CLKM
clock doubling PLLM
YINM UVINM
IFCM Input format conversion
VHCOMM Vertical and horizontal compression/ expansion
TSNR Temporal, spatial noise reduction
YINS UVINS
IFCS Input format conversion
VHCOMS Vertical and horizontal compression/ expansion
ED eDRAM + Buffer + Voltage control + Testcontroller
LM Line memory
SRCM Scan rate conversion Master Vertical expansion SRCS
M U X
DLTI DCTI Peaking
OFC 4:4:4 8:8:8 Framing Delay
DAC DAC DAC
YO UO VO YOUT UVOUT
CLKS
clock doubling PLLS
LM Line memory
ISCS Input sync controller Slave
SDA
SCL
Figure 1
Block diagram
The SDA 9415 contains the blocks, which will be briefly described below: ISCM/S - Flexible input sync controller IFCM/S - Input format conversion, Adjustable delay VHCOMM/S - Vertical and horizontal compression, horizontal expansion, panorama mode (only M) TSNR - Temporal and spatial noise reduction, noise measurement LBD - Letter box detection ME - Motion estimation, Film mode and phase detection MC - Memory controller OSCM/S - Flexible output sync controller OFC - Output format conversion, 4:4:4, 8:8:8 interpolation, Adjustable delay SRCM/S - Scan rate conversion, vertical expansion MUX - Combination of the two output channels DLTI/DCTI/Peaking - Luminance and chrominance transition improvement, luminance peaking I2C - IC bus interface PLLM/S/D - PLL for frequency doubling LM - Line memory core, VM - Vector memory core ED - eDRAM core
16
Micronas
bd9415
HINS VINS SYNCENS
MC Memory Controller
IC
SDA 9415 - B13
Preliminary Data Sheet
Block diagram
INPUT PROCESSING MASTER MOTION ESTIMATION FILM MODE DETECTION
OUTPUT PROCESSING MASTER
YINM UVINM
VERTICAL AND HORIZONTAL COMPRESSION/ HORIZONTAL EXPANSION VERT. PEAKING
3D SPATIO TEMPORAL NOISE REDUCTION
eDRAM VECTOR MEMORY
LINE TO BLOCK CONVERSION
DISPLAY PROCESSING SCAN RATE CONVERSION VERTICAL ZOOM BLOCK TO LINE CONVERSION DLTI DCTI PEAKING 8:8:8 INTERPOLATION Y0 TRIPLE DAC U0 V0
INPUT PROCESSING SLAVE VERTICAL AND HORIZONTAL COMPRESSION/ HORIZONTAL EXPANSION VERT. PEAKING
LETTER BOX DETECTION
eDRAM MAIN MEMORY
MUX OUTPUT PROCESSING SLAVE
YINS UVINS
SCAN RATE CONVERSION
YOUT UVOUT
HINM VINM HINS VINS
INPUT SYNC CONTROLLER
MEMORY CONTROLLER
OUTPUT SYNC CONTROLLER
HOUT VOUT BLANK
Figure 2
Block diagram 2
17
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Pin Description
4
Pin Description
Pin Diagram: P-MQFP-144-2 (top view)
098
097
091
086
085
081
105
103
101
095
094
093
090
088
084
083
082
078
077
075
074
108
107
106
104
102
100
099
096
092
089
087
080
079
076
073
N.C. N.C. SCL SDA VSSL6 VSSL7 VDDP5 VDDA3 VSSA3 CLKM VSSP6 UVOUT0 VSSL8 N.C. VSSL9 UVOUT1 UVOUT2 N.C. VDDE2 VSSL2 VDDL2 UVOUT3 N.C. UVOUT4 VDDP6 UVOUT5 VSSP7 UVOUT6 VDDL3 VSSL3 BLANK INTERLACED VOUT N.C. N.C. N.C.
N.C. N.C. N.C. VINM HINM SYNCENM VSSP5 UVINM0 UVINM1 UVINM2 UVINM3 UVINM4 UVINM5 VDDP4 UVINM6 UVINM7 YINM0 YINM1 YINM2 YINM3 VSSP4 N.C. YINM4 YINM5 YINM6 YINM7 UVINS0 UVINS1 UVINS2 UVINS3 UVINS4 UVINS5 VDDP3 N.C. N.C. N.C.
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 001 002 003 004 005 013 017 021 031 032 006 007 008 009 010 011 012 014 015 016 018 019 020 022 023 024 025 026 027 028 030 033 034 035 029 036
072 071 070 069 068 067 066 065 064 063 062 061 060 059 058 057 056 055 054 053 052 051 050 049 048 047 046 045 044 043 042 041 040 039 038 037
SDA 9415
HOUT CLKOUT X1/CLKD X2 UVOUT7 YOUT0 VSSP8 VDDP7 YOUT1 YOUT2 VSSA1 VDDA1 VSSA5 VDDA5 UREF_I RREF_I VSSA4 VDDV IV_O IVQ_O VDDY IY_O IYQ_O VDDU IU_O IUQ_O TEST RESET YOUT3 VDDP1 VSSP1 YOUT4 VINS N.C. N.C. N.C.
PIN49415
Figure 3
Pin configuration
18
N.C. N.C. N.C. UVINS6 UVINS7 VSSP3 CLKS VSSA2 VDDA2 YINS0 YINS1 YINS2 N.C. YINS3 N.C. YINS4 N.C. VDDE1 VSSE1 VDDL1 VDDP2 VSSP2 N.C. YINS5 YINS6 YINS7 YOUT7 VDDL4 VSSL4 YOUT6 YOUT5 SYNCENS HINS N.C. N.C. N.C.
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Pin Description
Table 1 Symbol
VSSLx *)
Pin definitions and functions Pin Num.
19, 29, 79, 89, 94, 96, 103, 104 20, 28, 80, 88, 90 6, 22, 42, 66, 82, 98, 115, 129 21, 43, 65, 84, 102, 122, 141 19 18, 90 8, 56, 60, 62, 100 9, 59, 61, 101 125,...,128; 131,...,134 116,...,121; 123;124 10,...,12;14; 16;24,...,26 135,...,140; 4;5 45
Input Outp.
S
Function
Supply voltage for digital logic parts ( VSS = 0 V )
VDDLx VSSPx
S S
Supply voltage for digital logic parts ( VDD = 3.3 V ) Supply voltage for pads ( VSS = 0 V )
VDDPx
S
Supply voltage for pads ( VDD = 3.3 V )
VSSE1 VDDEx VSSAx VDDAx YINM 0...7 UVINM 0...7 YINS 0...7 UVINS 0...7 RESET
S S S S I/TTL
Supply voltage for embedded DRAM ( VSS = 0 V ) Supply voltage for embedded DRAM ( VDD = 3.3 V ) Supply voltage for analog PLL and for analog parts DAC ( VSS = 0 V ) Supply voltage for analog PLL and for analog parts DAC ( VDD = 3.3 V ) Data input Y master channel
I/TTL PD Data input UV master channel I/TTL PD Data input Y slave channel I/TTL PD Data input UV slave channel I/TTL System reset. The RESET input is low active. In order to ensure correct operation a "Power On Reset" must be performed. The RESET pulse must have a minimum duration of two clock periods of the master (CLKM) and slave clock (CLKS), respectively. H-Sync input master channel V-Sync input master channel Synchronization enable input master channel H-Sync input slave channel V-Sync input slave channel Synchronization enable input slave channel I2C-Bus data line
HINM VINM SYNCENM HINS VINS SYNCENS SDA
113 112 114 33 40 32 105
I/TTL PD I/TTL PD I/TTL I/TTL PD I/TTL PD I/TTL IO
19
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Pin Description Table 1 Symbol
SCL BLANK VOUT HOUT
Pin definitions and functions (continued) Pin Num.
106 78 76 72
Input Outp.
I O/TTL O/TTL O/TTL O/TTL I/TTL I/TTL I/TTL O/ANA O/TTL I/TTL
Function
I2C-Bus clock line Blanking signal V-Sync output H-Sync output Interlace signal for AC coupled vertical deflection System clock master channel System clock slave channel Crystal connection / System clock display channel Crystal connection System clock output Test input, connect to VSS for normal operation Digital luminance output Digital chrominance output Analog luminance output Y Differential analog Y output, connect to VSS for normal operation Supply voltage for analog parts DAC ( VDD = 3.3 V ) Analog luminance output U Differential analog U output, connect to VSS for normal operation Supply voltage for analog parts DAC ( VDD = 3.3 V ) Analog luminance output V Differential analog V output, connect to VSS for normal operation Supply voltage for analog parts DAC ( VDD = 3.3 V ) Analog reference voltage for DACs Reference resistor for DACs
INTERLACED 77 CLKM CLKS X1 / CLKD X2 CLKOUT TEST YOUT7...0 UVOUT7...0 IY_O IYQ_O VDDY IU_O IUQ_O VDDU IV_O IVQ_O VDDV UREF_I RREF_I N.C. 99 7 70 69 71 46
27;30;31;41; O/TTL 44;63;64;67 68;81;83;85; O/TTL 87;92;93;97 51 50 52 48 47 49 54 53 55 58 57 1,2,3,13,15, 17,23,34,35, 36,37,38,39, 73,74,75,86, 91,95,107, 108,109, 110,111, 130,142, 143,144 O/ANA O/ANA S O/ANA O/ANA S O/ANA O/ANA S I/ANA
S: supply, I: input, O: output, TTL: digital (TTL) ANA: analog PD: pull down (switched on or off depending on IC bus parameter FORMATM, FORMATS or SLAVECON)
20
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Pin Description
*) x - placeholder for number
21
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Pin Description
22
Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
5
5.1
System description
Introduction
(R)
The SDA 9415 is the first single-chip Micronas MEGAVISION feature box including scan rate conversion and the necessary field memories, a second input channel for split screen applications like picture-and-picture and digital-to-analog converters. The SDA 9415 has three application modes: the SRC (Scan Rate Conversion) mode, the SSC (Split SCreen) mode and the MUP (MUlti Picture) mode. The two input channels of the SDA 9415 are not equivalent. One input channel is always the so called "master" channel and one input channel is always the so called "slave" channel. Both channels are combined of the output side of the SDA 9415 in the "MUX" block. The master channel is always the "synchronization" master of both channels. In the SRC mode the SDA 9415 can be used as a high performance scan rate converter. Scan rate conversion is done by a motion compensated algorithm known as Micronas VDU (Vector Driven Up conversion). In addition a high resolution frame based joint-linefree picture-and-picture (maximum approximately 1/9 picture) can be displayed. The figure below shows an example of the SRC mode.
Figure 4
Principles of SRC mode
23
Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description For this usage the 6 Mbit eDRAM core is separated in two luminance fields and two chrominance fields (either 4:2:0 or 4:1:1) and a memory area for luminance and chrominance fields (4:1:1) [maximum circa 1/9 picture] for picture-in-picture applications. The vector based scan rate conversion is possible for the master channel only. For the SSC mode the 6 Mbit eDRAM core is split in two 3 Mbit areas, which are able to contain a maximum of two luminance fields and two chrominance fields (either 4:2:0 or 4:1:1). The figure below shows different applications ("Double window", "Zoom-in-zoomout"). In this case only a simple scan rate conversion (e.g. field doubling for interlaced conversion: AABB) for both output channels is possible.
Figure 5
Principles of SSC mode
24
Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description The MUP mode allows the combination of one life picture and a configuration of still pictures. The figure below shows an application. In this case only a simple scan rate conversion (e.g. field doubling for interlaced conversion: AABB or AAAA) is possible.
Figure 6
Principles of MUP mode
The behaviour of the master and the slave channel does not differ in general. Therefore for further description of the master and the slave channel the figures are also valid for both unless it is pointed out.
25
Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
5.2
Input sync controller (ISCM/ISCS)
Signals HINM VINM SYNCENM HINS VINS SYNCENS
Pin number 27 26 28 77 78 76
Description horizontal synchronization signal (polarity programmable, IC Bus parameter 11h HINPOLM, default: high active) vertical synchronization signal (polarity programmable, IC Bus parameter 11h VINPOLM, default: high active) enable signal for HINM and VINM signal, low active ("Input format conversion (IFCM/IFCS)" on page 30) horizontal synchronization signal (polarity programmable, IC Bus parameter 33h HINPOLS, default: high active) vertical synchronization signal (polarity programmable, IC Bus parameter 33h VINPOLS, default: high active) enable signal for HINS and VINS signal, low active ("Input format conversion (IFCM/IFCS)" on page 30)
Table 2
Input signals
The input sync controller derives framing signals from the H- and V-Sync for the input data processing. The framing signals depend on different IC Bus parameters and mark the active picture area.
HINM pixels per line VINM lines per field
NALIPM + PD
(ALPFIPM*2)
(APPLIPM*8)*CLKM (NAPIPDLM*4 + NAPIPPHM+PD)* CLKM PD - Processing Delay
Figure 7
Input IC Bus parameter
The distance between the incoming H-syncs in system clocks of CLKM/CLKS must be even.
26 Micronas
inpar01
SDA 9415 - B13
Preliminary Data Sheet
System description
IC Bus parameter [Default value] NALIPM [20] NALIPS [20] ALPFIPM [144] ALPFIPS [144] NAPLIPM NAPIPDLM [0] NAPIPPHM [0] NAPLIPS NAPIPDLS [0] NAPIPPHS [0] APPLIPM [180] APPLIPS [180]
Sub address 12h 34h 10h 32h 03h, 0Ch
Description Not Active Line InPut Master defines the number of lines from the V-Sync to the first active line of the field Not Active Line InPut Slave defines the number of lines from the V-Sync to the first active line of the field Active Lines Per Field InPut Master defines the number of active lines Active Lines Per Field InPut Slave defines the number of active lines Not Active Pixels Per Line InPut Master defines the number of pixels from the H-Sync to the first active pixel of the line. The number of pixels is a combination of NAPIPDLM and NAPIPPHM. Not Active Pixels Per Line InPut defines the number of pixels from the H-Sync to the first active pixel of the line. The number of pixels is a combination of NAPIPDLS and NAPIPPHS.
2Dh, 2Eh
0Fh 31h
Active Pixels Per Line InPut Master defines the number of active pixels Active Pixels Per Line InPut Slave defines the number of active pixels
Table 3
Input write IC Bus parameter
Inside of the SDA 9415 a field detection block is necessary for the detection of an odd (A) or even (B) field. Therefore the incoming H-Sync H1 (delayed HINM/HINS signal, delay depends on NAPIPDLM/NAPIPDLS and NAPIPPHM/NAPIPPHS) is doubled (H2 signal). Depending on the phase position of the rising edge of the VINM/VINS signal an A (rising edge between H1 and H2) or B (rising edge between H2 and H1) field is detected. For proper operation of the field detection block, the VINM/VINS must be delayed depending on the delay of the HINM/HINS signal (H1). The figure below explains the field detection process and the functionality of the VINDELM/VINDELS IC Bus parameter (inside the SDA 9415 the delayed VINM/VINS signal is called Vd and the detected field signal is called Ffd).
27
Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
CLKM H1 H2 VINM Vd Ffd
x
(VINDELM * 128 + 1) * Tclkm Field 1(A)
VINM Vd Ffd
x
(VINDELM * 128 + 1) * Tclkm Field 2(B)
Figure 8
Field detection and VINM delay
IC Bus parameter [Default value] VINDELM [0] VINDELS [0] FIEINVM 1 : Field A=1 [0]: Field A=0 FIEINVS 1 : Field A=1 [0]: Field A=0 VCRMODEM [1]: on 0 : off VCRMODES [1]: on 0 : off
Sub address 11h 33h 0Bh
Description Delay of the incoming V-Sync VINM (must be adjusted depending on the delay of the HINM signal) Delay of the incoming V-Sync VINS (must be adjusted depending on the delay of the HINS signal) Inversion of the internal field polarity master
2Dh
Inversion of the internal field polarity slave
0Bh
In case of non standard interlaced signals (VCR, PlayStations) a filtering of the internal field signal has to be done (should also be used for normal TV signals) In case of non standard interlaced signals (VCR, PlayStations) a filtering of the internal field signal has to be done (should also be used for normal TV signals)
2Dh
Table 4
Input write IC Bus parameter
In case of non-standard signals the field order is indeterminate (e.g. AAA... , BBB... , AAABAAAB..., etc.). Therefore a special filtering algorithm is implemented, which can be switched on by the IC Bus parameter VCRMODEM/VCRMODES. It is recommended to set the IC Bus parameter VCRMODEM=1. In other case (VCRMODEM=0) an additional
28
Micronas
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Preliminary Data Sheet
System description internal signal VTSEQM is generated. This signal level is high (VTSEQM=1), if at least the last to fields were identical. Due to the fixed storage places of the fields in the internal memory block, this information is necessary for the scan rate conversion processing ("Output sync controller (OSCM/S)" on page 81, it is recommended in case of VCRMODEM=0 to choose an adaptive operation mode). The OPDELM IC Bus parameter is used to adjust the outgoing V-Sync VOUT in relation to the incoming delayed V-Sync VINM. In case of SSC and MUP mode the recommended default value should not be changed.
IC Bus parameter [Default value] OPDELM [170]
Sub address 1Bh
Description Delay (in number of lines) of the internal V-Sync (delayed VINM) to the outgoing V-Sync (VOUT)
Table 5
Input write IC Bus parameter
The internal line counter is used to determine the information about the standard of the incoming signal.
IC Bus parameter TVMODEM
Sub address 7Bh
Description TV standard of the incoming signal master: 1: NTSC 0: PAL TV standard of the incoming signal slave: 1: NTSC 0: PAL
TVMODES
7Dh
Table 6
Input read IC Bus parameter
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Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
5.3
Input format conversion (IFCM/IFCS)
Signals YINM0...7 UVINM0...7 YINS0...7 UVINS0...7
Pin number 39,40,41,42,44,45,46,47 30,31,32,33,34,35,37.38 61,62,63,64,65,71,72,73 48,49,50,51,52,53,55,56
Description luminance input master chrominance input master luminance input slave chrominance input slave
Table 7
Input signals
The SDA 9415 accepts at the input side the sample frequency relations of Y : (B-Y) : (R-Y): 4:2:2 and CCIR 656.
Data Pin
CCIR 656 FORMATM = 1X FORMATM = 01
4:2:2 Parallel FORMATM = 00 V07 V06 V05 V04 V03 V02 V01 V00 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 U07 U06 U05 U04 U03 U02 U01 U00 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 V07 V06 V05 V04 V03 V02 V01 V00
YINM7 YINM6 YINM5 YINM4 YINM3 YINM2 YINM1 YINM0 UVINM7 UVINM6 UVINM5 UVINM4 UVINM3 UVINM2 UVINM1 UVINM0
U07 U06 U05 U04 U03 U02 U01 U00
Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00
Table 8
Input data formats
Xab: X: signal component a: sample number b: bit number
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Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description In case of CCIR 656 three modes are supported (FORMATM/FORMATS=11 means full CCIR 656 support, including H-, V-Sync and Field signal, FORMATM/FORMATS=01 means only data processing, H- and V-Sync have to be added separately according PAL/NTSC norm, FORMATM/FORMATS=10 means only data processing, H- and Vsync have to be added separately according CCIR656-PAL/NTSC norm). The representation of the samples of the chrominance signal is programmable as positive dual code (unsigned, IC Bus parameter TWOINM/TWOINS=0) or two's complement code (TWOINM/TWOINS=1, "IC Bus" on page 123, IC Bus parameter 0Bh,2Dh). Inside the SDA 9415 all algorithms assume positive dual code.
FORMATM/ FORMATS 00 01 (CCIR 656 only data) 10 11 (full CCIR 656)
HINS/HINS PAL/NTSC PAL/NTSC CCIR 656 x
VINM/VINS PAL/NTSC PAL/NTSC CCIR 656 x
YINM/YINS 4:2:2 CCIR 656 CCIR 656 CCIR 656
UVINM/UVINS 4:2:2 x x x
Table 9
Input sync formats
The amplitude resolution for each input signal component is 8 bit, the maximum clock frequency is 27 MHz. Consequently the SDA 9415 is dedicated for application in high quality digital video systems.
31
Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description The Figure 9 shows the generation of the internal H- and V-syncs in case of full CCIR 656 mode. The H656 sync is generated after the EAV. The V656 and F656 signals change synchronously with the EAV timing reference code.
CLK1 (27 MHz) CCIR 656 interface YIN
EAV SAV u0 y0 v0 y1 u2 y3 EAV
288 Tclk1(PAL) 276 Tclk1(NTSC) 1728 Tclk1(PAL) 1716 Tclk1(NTSC)
CLK1 (27 MHz) YIN H656 V656 (e.g.) F656 (e.g.)
EAV 11111111 00000000 00000000 1FV1P3P2P1P0 x EAV x x SAV x x EAV x
F = 0 during field 1(A) F = 1 during field 2(B)
MSB
LSB
SAV 11111111 00000000 00000000 1FV0P3P2P1P0
V = 0 elsewhere V = 1 during field blanking
Figure 9
Explanation of 656 format
The Figure 10 explains the functionality of the SYNCENM/SYNCENS signal. The SDA 9415 needs the SYNCENM/SYNCENS (synchronization enable) signal, which is used to gate the YINM/YINS, UVINM/UVINS as well as the HINM/HINS and the VINM/VINS signal. This is implemented for frontends which are working with 13.5 MHz and a large output delay time for YINM/YINS, UVINM/UVINS, HINM/HINS and VINM/VINS (e.g. Micronas VPC32XX, output delay: 35 ns). For this application the half system clock CLKM/CLKS (13.5 MHz) from the frontend should be provided at this pin. In case the frontend is working at 27.0 MHz with sync signals having delay times smaller than 25 ns, this input can be set to low level (SYNCENM/SYNCENS=VSS) (e.g. Micronas SDA 9206, output delay: 25 ns). Thus the signals YINM/YINS, UVINM/UVINS, HINM/HINS and VINM/VINS are sampled with the CLKM/CLKS system clock when the SYNCENM/ SYNCENS input is low. The Figure 10 shows the gated inputs signals YINMen, UVINMen, HINMen and VINMen.
32
Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
CLKM SYNCENM YINM UVINM YINMen UVINMen HINM/VINM HINMen/VINMen
x x y0 u0 y1 v0 y2 u2 y3 v2
x x
y0 u0
y1 v0
y2 u2
y3 v2
Figure 10
SYNCENM/SYNCENS signal
The Figure 11 shows the input timing and the functionality of the NAPIPDLM/NAPIPDLS and NAPIPPHM/NAPIPPHS IC Bus parameter in case of CCIR 656 and 4:2:2 parallel data input format for one example. The signals HINMint, YINMint and UVMint are the internal available sampled input signals.
CLKM HINM HINMint CCIR 656 interface YINM
xxx u0 y0 u0 y0 u0 v0 y1 v0 y1 v0 u2 y2 u2 y2 u2 v2 y3 v2 y3 v2 u4 y4 u4
(NAPIPDLM* 4 + NAPIPPHM + 7) * Tclkm =(0 * 4 + 2 + 7) * Tclkm = 9 Tclkm (e.g.) YINMint UVINMint 4:2:2 interface YINM UVINM YINMint UVINMint
xxx xxx y0 u0
(NAPIPDLM* 4 + NAPIPPHM + 7) * Tclkm =(0 * 4 + 3 + 7) * Tclkm = 10 Tclkm (e.g.)
y1 v0 y0 u0
y2 u2 y1 v0
y3 v2 y3 u2
y4 u4 y4 v2
Figure 11
Input timing
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Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
5.4
Input signal processing
The Figure 12 shows a detailed block diagram of the input processing blocks. The input signal can be vertically and horizontally compressed or horizontally expanded by a large number of factors. Furthermore the input signal can be processed by different noise reduction algorithms to reduce the noise in the signal. The noise measurement block determines the noise level of the input signal. The letter box detection block finds the start and end line of letter box pictures. The information can be used by a C to calculate zooming factors and to control the IC for resizing the picture for a full screen display on 16:9 tubes.
NMLINE, NMALG NOISEME MASTER
Letter box detection Noise measurement
SNRON
NRON
DELM YINM UVINM
Delay -3/+4 Line memories
Vertical and horizontal compression/ expansion
YM from Memory
Spatial noise reduction Temporal noise reduction
YM to Memory CM to Memory CM from Memory bdldr01 YS to Memory CS to Memory
SLAVE YINS UVINS
Delay -3/+4 Line memories
Vertical and horizontal compression/ expansion
DELS
Figure 12
Block diagram of input processing blocks
The different blocks and the corresponding IC Bus parameters will be described now in more detail.
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Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
5.4.1
Adjustable delay
It is possible to adjust the luminance signal in relation to the chrominance signal in (CLKM/CLKS) steps. For further processing it is important, that the luminance signal and the chrominance signal are adjusted. Adjustment may be necessary, if the luminance and chrominance signal generated by the frontend processor are not adjusted.
DELM/DELS (04h,026h) 0 1 2 3 4 5 6 7
Delay between luminance and chrominance data in steps of 27.0 MHz (CLKM/CLKS) -3 -2 -1 0 +1 +2 +3 +4
Table 10
DELM/DELS IC Bus parameter
35
Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
5.4.2
Vertical and horizontal compression (VHCOMM/VHCOMS)
The Figure 13 shows the block diagram of the VHCOMM and VHCOMS block. The VHCOMM and VHCOMS block are able to compress the picture in horizontal and vertical direction continuously. The minimal step size in vertical direction is two lines, the minimal step size in horizontal direction is four pixels. The figure below shows also the functionality and the formula, which shows the relation between the number of input lines (pixels) and output lines (pixels). In horizontal direction an expansion is also possible. Panorama mode in horizontal direction will be supported.
INTVM, INTVS, DEZVM, DEZVS, CHFILM, CHFILS
Vertical compression
YPEAKM, CPEAKM, YPEAKS, CPEAKS
Vertical peaking
INTHM, INTHS, DEZHM, DEZHS
Horizontal compression/ expansion
vhcombd
YUVIN
YUVOUT
4*APPLIPM 4*APPLIPS pixels (CLKM/2)
4*APPLIPM 4*APPLIPS pixels (CLKM/2)
4*APPLM 4*APPLS pixels (CLKM/2)
2*ALPFIPM, 2*ALPFIPS lines
2*ALPFM 2*ALPFS lines
Number of output lines = (Number of input lines) * 512 / (512+INTVM) * 1/(DEZVM)
INTVM = 0, ..., 511; DEZVM = {1, 2, 4, 8, 16} INTHM = 2048, ... , 8191; DEZHM = {1, 2, 4, 8, 16}
Number of output lines = (Number of input lines) * 2 * 2048 / (INTHM) * 1/(DEZHM)
Figure 13
Block diagram of VHCOMM/VHCOMS
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Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
5.4.2.1
Vertical compression and peaking
The overall reduction of the vertical compression block can be calculated by the formula:
512 1 ---------------------------------------- -------------------- 512 + INTVM DEZVM
The user must specify the vertical input picture size (defined by IC Bus parameter ALPFIPM/ALPFIPS) and the vertical output picture size (defined by IC Bus parameter APPLM/APPLS) as well as the IC Bus parameter INTVM/INTVS (IC Bus parameter, 09h,0Ah,2Bh,2Ch) and DEZVM/DEZVS (IC Bus parameter, 0Ah,2Ch), which can be calculated with the algorithm listed below (C-code). intV, dezV: variables for( intV=2*ALPFM/S, dezV=1; intV<=2*ALPFIPM/S; intV*=2, dezV*=2 ) ; intV = ((512*2*ALPFIPM/S*2+intV/2)/intV); dezV/=2; if(dezV>16) { intV=intV*dezV/16; dezV=16; } INTVM/S=intV-512;
37
Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
Vertical line size 2*ALPFM/S (2*ALPFIPM/S=288) 288
INTVM/S
dezV/DEZVM/S
Comment
0
1/1
largest size, bypass recommended DEZVM/ DEZVS=0
216 192 145 144 96 73 72 36 18 10
171 256 505 0 256 497 0 0 0 409
1/1 1/1 1/1 2/4 2/4 2/4 4/5 8/6 16/7 16/7 smallest size PIP (1/3 picture) Double window
Table 11
Examples of vertical filter adjustment
dezV 16 8 4 2 1
DEZVM / DEZVS 111 110 101 100 001
Table 12
Conversion table between dezV and DEZVM / DEZVS
The vertical compression block can be switched off by setting DEZVM/DEZVS equal "0" and INTVM/INTVS=0. In this case it is possible to switch on a low pass filter for the chrominance data path by the IC Bus parameter CHFILM/CHFILS (IC Bus parameter, 03h, 25h). If CHFILM/CHFILS is equal to "0" or "2" the vertical filter for the chrominance is switched off. If CHFILM/CHFILS is equal to "1" or "3" the vertical filter for the chrominance is switched on (Table 17 "Input write IC Bus parameter CHFILM/ CHFILS" on page 42). In addition a vertical peaking of the input signal is possible.
38 Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
IC Bus parameter YPEAKM/YPEAKS CPEAKM/CPEAKS
0 (minimum value) peaking off peaking off
3 (maximum value) maximum peaking factor maximum peaking factor
Table 13
Input write IC Bus parameter YPEAKM/YPEAKS/CPEAKM/CPEAKS
IC Bus parameter INTVM DEZVM INTVS DEZVS YPEAKM CPEAKM YPEAKS CPEAKS ALPFM ALPFS CHFILM CHFILS
Sub address 09h,0Ah 0Ah 2Bh,2Ch 2Ch 0Ah 0Ah 2Ch 2Ch 0Dh 2Fh 03h 25h
Description Interpolation factor for vertical compression master Decimation factor for vertical compression master Interpolation factor for vertical compression slave Decimation factor for vertical compression master Vertical peaking factor for luminance signal master Vertical peaking factor for chrominance signal master Vertical peaking factor for luminance signal slave Vertical peaking factor for chrominance signal slave Number of active lines per field after vertical compression master Number of active lines per field after vertical compression slave Chrominance filter master channel on/off Chrominance filter slave channel on/off
Table 14
Input write IC Bus parameter
39
Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
5.4.2.2
Horizontal compression/expansion and panorama mode
The overall reduction of the horizontal compression block can be calculated by the formula:
2048 1 2 ------------------- --------------------INTHM DEZHM
The user must specify the horizontal input picture size (defined by the IC Bus parameter APPLIPM/APPLIPS) and the horizontal output picture size (defined by the IC Bus parameter APPLM/APPLS) as well as the IC Bus parameter INTHM/INTHS (IC Bus parameter, 07h, 08h, 29h, 2Ah) and DEZHM/DEZHS (IC Bus parameter, 08h, 2Ah), which can be calculated with the algorithm listed below (C-code). intV, dezV: variables for( intH=4*APPLM/S, dezH=1; intH<=4*APPLIPM/S; intH*=2, dezH*=2 ) ; intH = ((2048*4*APPLIPM/S*2+intH/2)/intH); if( dezH>16) { intH= intH*dezH/16; dezH=16; } INTHM/S = intH
40
Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
Horizontal pixel size (related to CLKM/2) 4*APPLM (4*APPLIPM=720) 1440 724 720 540 364 360 184 180 92 90 48 24
intH
dezH/ DEZHM/S
Comment
2048 4073 2048 2731 4050 2048 4007 2048 4007 2048 3840 7680
1/1 1/1 2/4 2/4 2/4 4/5 4/5 8/6 8/6 16/7 16/7 16/7
largest size, only 720 will be stored largest size, only 720 will be stored bypass recommended DEZHM/DEZHS=0 4:3 picture on 16:9 tube
Double window
smallest size
Table 15
Examples of horizontal filter adjustment
dezH 16 8 4 2 1
DEZHM/S 111 110 101 100 001
Table 16
Conversion table between dezH and DEZHM/DEZMS
The horizontal compression/expansion block can be switched off by setting DEZHM/ DEZHS equal "0" and INTHM/INTHS=2048. In this case it is possible to switch on a low pass filter for the chrominance data path by the IC Bus parameter CHFILM/CHFILS (IC Bus parameter, 03h,25h). If CHFILM/CHFILS is equal to "0" or "1" the horizontal filter for the chrominance is switched off. If CHFILM/CHFILS is equal to "2" or "3" the horizontal filter for the chrominance is switched on. The table below shows the different settings of CHFILM/S.
41
Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
CHFILM/CHFILMS 11 10 01 00
Vertical low pass filter (only valid for DEZVM/DEZVS=0) Vertical filter on Vertical filter off Vertical filter on Vertical filter off
Horizontal low pass filter (only valid for DEZHM/DEZHS=0) Horizontal filter on Horizontal filter on Horizontal filter off Horizontal filter off
Table 17
Input write IC Bus parameter CHFILM/CHFILS
In case of panorama mode the compression/expansion factor varies over one line. The figure below shows some examples.
Compression
PANAST+1
1.0
Expansion
Figure 14
Principles of panorama mode
Different settings of the IC Bus parameters INTHM/INTHS and DEZHM/DEZHS are necessary. The table below defines the settings:
PANAON 0 1
dezH DEZHM/DEZHS 1
intH INTHM INTHM (4096 recommended)
Table 18
Filter IC Bus parameter in case of PANAON=1
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Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
IC Bus parameter PANAST
0 (minimum value) slight panorama
15 (maximum value) strong panorama
Table 19
IC Bus parameter PANAST in case of PANAON=1
IC Bus parameter INTHM DEZHM INTHS DEZHS APPLM
Sub address 07h,08h 08h 29h,2Ah 2Ah 0Eh
Description Interpolation factor for horizontal compression/expansion master Decimation factor for horizontal compression/ expansion master Interpolation factor for horizontal compression/expansion slave Decimation factor for horizontal compression/ expansion slave Number of active pixels per line in the input data stream after horizontal compression/ expansion master Number of active pixels per line in the input data stream after horizontal compression/ expansion slave Horizontal panorama mode on/off Gradient of horizontal panorama mode
APPLS
30h
PANAON PANAST
1Ah 1Ah
Table 20
Input write IC Bus parameter
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Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
5.4.3
Noise reduction
The figure below shows a block diagram of the spatial and temporal motion adaptive noise reduction (first order IIR filter). The spatial noise reduction is only performed on the luminance signal. The structure of the temporal motion adaptive noise reduction is the same for the luminance as for the chrominance signal.
SNRON
YR YIN TNRCLY, TNRHOY, TNRKOY, TNRVAY, TNRFIY, NRON TNRCLC, TNRHOC, TNRKOC, TNRVAC, TNRFIC, NRON UVIN UVSNR UV1 Spatial noise reduction YSNR DY Motion detector KY Frame delay Field delay 1 0 DTNRON YOUT UVOUT Motion KUV detector 1 DUV Field delay Frame delay TNRSEL 0 1 DTNRON nr01
0
Figure 15
Block diagram of noise reduction
5.4.3.1
Spatial noise reduction
Normally a spatial noise reduction reduces the resolution due to the low pass characteristic of the used filter. Therefore the spatial noise reduction of the SDA 9415 works adaptive on the picture content. The low pas filter process is only executed on a homogeneous area.
IC Bus parameter SNRON 1: on 0: off
Sub address 1Ah
Description Spatial noise reduction of luminance signal
Table 21
Input write IC Bus parameter
44
Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
5.4.3.2
Motion adaptive temporal noise reduction
The equation below describes the behaviour of the temporal motion adaptive noise reduction filter. The same equation is valid for the chrominance signal. Depending on the motion in the input signal, the K-factor Ky (Kuv) can be adjusted between 0 (no motion) and 15 (motion) by the motion detector. The K-factor for the chrominance filter can be either Ky (output of the luminance motion detector, TNRSEL=0) or Kuv (output of the chrominance motion detector, TNRSEL=1). For the luminance and chrominance signal the delay of the feed back path can be either a field delay (DTNRON=1) or a frame delay (DTNRON=0) (block diagram of noise reduction).
Equation for temporal noise reduction (luminance signal)
1 + Ky YOUT = ae ----------------o YSNR - YR + YR 16
Equation for temporal noise reduction (chrominance signal)
1+K UVOUT = ae ------------ o UVSNR - UV1 + UV1 ;K = Ky ;Kuv 16
(compare "Block diagram of noise reduction" on page 44) The Figure 16 shows the motion detector in more detail. Temporal noise reduction can be switched off by NRON (NRON=0). The IC Bus parameter TNRFIY/C switches between a fixed noise reduction K-factor TNRVAY/C (TNRFIY/C=0) or a motion adaptive noise reduction K-factor (TNRFIY/C=1).
TNRCLY/C+1 TNRKOY/C+1 TNRFIY/C NRON
Motion DY/UV Motion detection LUT
0 1
MUX
0
1
MUX 15
0
Ky/uv nr01
TNRHOY/C TNRVAY/C
Figure 16
Block diagram of motion detector
In case of adaptive noise reduction the K-factor depends on the detected "Motion" (see Figure 16). The "Motion"-Ky/Kuv characteristic curve (LUT) is fixed inside the SDA 9415, but the characteristic curve can be changed by two IC Bus parameters: TNRHOY/ C and TNRKOY/C. TNRHOY/C shifts the curve horizontally and TNRKOY/C shifts the
45 Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description curve vertically. For a fixed characteristic curve, the sensitivity of the motion detector is adjustable by TNRCLY/C.
TNRKOY/C=7 TNRHOY/C=0 TNRKOY/C=-1 TNRHOY/C=0 10 TNRKOY/C
Ky/Kuv 15
5
TNRKOY/C=-8 TNRHOY/C=0
Motion 5 10 15 20 25 30
Ky/Kuv 15
TNRKOY/C=-1 TNRHOY/C=15 TNRKOY/C=-1 TNRHOY/C=0
10 TNRHOY/C TNRKOY/C=-1 TNRHOY/C=-15
5
Motion 5
Figure 17
10
15
20
25
30
LUT for motion detection
46
nr03
Micronas
nr02
SDA 9415 - B13
Preliminary Data Sheet
System description
IC Bus parameter TNRVAY/C
0 (minimum value) strong noise reduction (not motion adaptive, Ky/Kuv=0)
15 (maximum value) no noise reduction (not motion adaptive, Ky/Kuv=15)
Table 22
IC Bus parameter TNRVAY/C
IC Bus parameter TNRHOY/C TNRKOY/C
Range -32, ... , 31 -8, ..., 7
Table 23
IC Bus parameter TNRHOY/C and TNRKOY/C
IC Bus parameter TNRCLY/C
0 (minimum value) maximum sensitivity for motion -> strong noise reduction
15 (maximum value) minimum sensitivity for motion -> weak noise reduction
Table 24
IC Bus parameter TNRCLY
47
Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
IC Bus parameter NRON 1: on 0: off TNRSEL 1: separate 0: luminance motion detector DTNRON 1: field 0: frame TNRFIY/C 1: off 0: on TNRVAY/C TNRHOY/C TNRKOY/C TNRCLY/C
Sub address 1Ah
Description Temporal Noise Reduction of Luminance and Chrominance On (SRC-Mode) Switch for motion detection of temporal noise reduction of chrominance signal
18h
1Ah
Delay for temporal noise reduction of luminance and chrominance signal Switch for fixed K-factor value defined by TNRVAY/C
18h/19h
17h 18h/19h 16h 15h
Fixed K-factor for temporal noise reduction of luminance/chrominance Horizontal shift of the motion detector characteristic Vertical shift of the motion detector characteristic Classification of temporal noise reduction
Table 25
Input write IC Bus parameter
5.4.4
Noise measurement
The noise measurement algorithm can be used to change the IC Bus parameters of the temporal noise reduction processing depending on the actual noise level of the input signal. This is done by the IC Bus controller which reads the NOISEME value, and sends depending on this value different IC Bus parameter sets to the temporal noise reduction registers of the SDA 9415. The NOISEME value can be interpreted as a linear curve from no noise (0) to strong noise (30). Value 31 indicates an overflow status and can be handled in different ways: strong noise or measurement failed. Two measurement algorithms are included, which can be chosen by the IC Bus parameter NMALG. In case NMALG=1 the noise is measured during the vertical blanking period in the line defined by NMLINE. For NMALG=0 the noise is measured during the first active line. In the latter case the delay of the noise reduction algorithm must be set to the frame difference value (DTNRON=0, IC Bus sub address 1Ah). In both cases the value is determined by averaging over several fields. The Figure 18 shows an example for the noise measurement. The NMLINE IC Bus parameter determines the line, which is used in the SDA 9415 for the measurement. In case of VINDEL=0 and NMLINE=0 line 3 of the field A and line 316 of the field B is
48
Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description chosen. In case of VINDEL=0 and NMLINE=3 line 6 of the field A and line 319 of the field B is chosen.
Field1 (A) 1
623 H-sync V-sync
624
625
2
3
4
5
6
7
VINDEL=0 Measure NMLINE=0 NMLINE=3
: :
Measure
310 H-sync V-sync
311
312
Field2 (B) 313-1
314-2
315-3
316-4
317-5
318-6
319-7
VINDEL=0 Measure NMLINE=0 NMLINE=3
: :
Measure
PAL
Figure 18
Example of noise measurement
IC Bus parameter NMALG
Sub address 14h
Description Noise measurement algorithm 1: measurement during vertical blanking period (measure line can be defined by NMLINE) 0: measurement in the first active line Line for noise measurement (only valid for NMALG=1)
NMLINE
14h
Table 26
Input write IC Bus parameter
49
Micronas
NM01
SDA 9415 - B13
Preliminary Data Sheet
System description
IC Bus parameter NOISEME NMSTATUS
Sub address 7Ah 7Ch
Description Noise level of the input signal: 0 (no noise), ... , 30 (strong noise) [31 (strong noise or measurement failed)] Signals a new value for NOISEME 1: a new value can be read 0: current noise measurement has not been updated ("IC Bus" on page 123)
Table 27
Input read IC Bus parameter
5.4.5
Letter box detection
The Figure 19 shows the display of a 4:3 letter box source on 16:9 tube. Black bars on the top and bottom as well as on the right and on the left are visible. It is possible by vertical and horizontal expansion to display the picture on the whole tube. Therefore only the first line (Start Line of Active Area - SLAA) and the last line (End Line of Active Area - ELAA) of the active area must be known. The letter box detection algorithm detects SLAA and ELAA. Both IC Bus parameters can be read out via IC Bus. The C of the TV chassis can use both values to calculate the corresponding zoom factor for the vertical expansion.
SLAA Vertical and horizontal expansion ELAA
lbd
Figure 19
Principle of letter box detection
The Figure 20 shows the block diagram of the letter box detection. The letter box algorithm processes only the luminance data. Each incoming field is processed. The default value of SLAA is NALPFIPM+PD and of ELAA is 2*ALPFIPM+NALPFIPM+PD-1 (PD - Processing Delay), which means no letter box format source material.
50
Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
TH_AA TH_LB
SLAA TH_DN_BN Line Type Decision LT Processing Start/Endline Decision Status_SLAA ELAA Status_ELAA Reliability Evaluation
lbdbd
YINM
Histogram
RELY
TH_MUNSL, TH_AUNS TH_ALB, TH_MA_AA
Figure 20
Block diagram of letter box detection
Each line of the input picture will be assigned to one of three line types (LT) by the "Histogram" and "Line Type decision" block. The figure below shows in detail the functionality of both blocks. The "Histogram" block counts the amount of pixels (BC), which are larger or equal 2*TH_DN_BN (IC Bus parameter, 1Ch). Depending on the counter value the line is assigned to one of the three line types by the "Line Type Decision" block. The IC parameter TH_AA and TH_LB can be used to influence the result of the "Line Type Decision" block.
Line Type (LT) AA LB UNS
Priority 1 2 3
BC >= 4 * TH_AA < 4 * TH_LB < 4 * TH_AA and >= 4 * TH_LB
Table 28
Line Type Decision of LBD
The line type AA marks lines which belong to an active area, the line type LB marks lines which belong to a letter box area (maybe including logos, subtitles) and the line type UNS marks lines which could not assigned with security to one of both line types mentioned before.
51
Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
Histogram
Pixel Value 2* TH_DN_BN Amount of Pixels > 2*TH_DN_BN BC
APPLIPM*4
Line Type Decision
AA 4 * TH_AA
... ... ... ...
line
BC
UNS
0
lbdHLD
4 * TH_LB LB
TH_DN_BN (IC bus parameter)
Figure 21
Histogram and line type decision
Based on the line types the first line of the active area (SLAA, IC parameter 78h) and the last line of the active area (ELAA, IC parameter 79h) is determined. Furthermore the information about reliability of the SLAA and ELAA value is determined. The reliability information is readable by IC Bus of the parameters STATUS_SLAA and STATUS_ELAA. If STATUS_SLAA/STATUS_ELAA is equal "1" the SLAA/ELAA value is reliable, otherwise the SLAA/ELAA value is not reliable. In addition a global reliability signal RELY exists, which is also readable by IC Bus. The results of the letter box detection are reliable, if the RELY signal is read as "1". The "Reliability evaluation" block determines the RELY signal, which can be influenced by the IC Bus parameter TH_MUNSL, TH_AUNS and TH_ALB. The table below explains the generation of the RELY signal. The thresholds TH_MUNSL, TH_AUNS and TH_ALB are compared with internal counter values UNSLENGTH, UNSAMOUNT and LBAMOUNT, respectively. If one of the three conditions is true, the RELY signal is set to not reliable. UNSLENGTH contains the maximum length of consecutive lines with the line type UNS. UNSAMOUNT contains the amount of lines with the line type UNS and LBAMOUNT contains the amount of lines with the line type LB.
RELY 0 (not reliable) 1 (reliable) UNSLENGTH > 16 * TH_MUNSL or UNSAMOUNT > 16 * TH_AUNS or LBAMOUNT > 16 *TH_ALB otherwise
Table 29
Evaluation of the reliability signal RELY
The IC Bus parameter TH_MA_AA can be used to force the SLAA and ELAA value to their default values. Therefore the amount of active area line types AA is counted in the
52 Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description upper half of the input picture (AAFH) and the lower half of the input picture (AASH). If one of both counter values is greater as 2*TH_MA_AA + 112, the SLAA and ELAA IC Bus parameters are set to their default values.
Output signals SLAA=NALPIPM+PD ELAA=2*ALPFIPM+SLAA-1 Status_SLAA=TRUE Status_ELAA=TRUE no change of the values (AAFH or AASH) >= 2 * TH_MA_AA + 112
otherwise
Table 30
Correction of "start/end-line decision filter" block
It is possible to make the results of the letter box detection visible on screen in real time to optimize the IC Bus parameters. The figure below explains the different possibilities. The IC Bus parameter VOLBD can be used to switch on (VOLBD=1) or off (VOLBD=0) the visibility function.
PANATV
SLAA, Status_SLAA=FALSE RELY=FALSE
PANATV
SLAA, Status_SLAA=TRUE RELY=FALSE
this is a letter box
ELAA, Status_ELAA=FALSE
this is a letter box
ELAA, Status_ELAA=TRUE
PANATV
SLAA, Status_SLAA=FALSE RELY=TRUE
PANATV
SLAA, Status_SLAA=TRUE RELY=TRUE
this is a letter box
Figure 22
Visibility of letter box detection IC Bus parameters
53
lbdvis
ELAA, Status_ELAA=FALSE
this is a letter box
ELAA, Status_ELAA=TRUE
Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
IC Bus parameter [default] TH_DN_BN [15] TH_LB [12] TH_ALB [6] TH_AA [50] TH_MUNSL [5] TH_AUNS [7] TH_MA_AA [14] VOLBD [0]
Sub address
Description
1Ch 1Ch,1Dh 1Dh 1Eh 1Fh 1Fh 20h 20h
Darkness Brightness threshold Letter box threshold Amount of letter box threshold Active area threshold Maximum length of insecure threshold Amount of letter box and insecure threshold Maximum amount of active area threshold Makes result of letter box detection visible on screen 1: on 0: off
Table 31
IC Bus parameter SLAA ELAA
Input write IC Bus parameter
Sub address 78h 79h 7Bh Description First line of active area = 2 * SLAA Last line of active area = 2 * ELAA Status of SLAA 1: SLAA is reliable 0: SLAA is not reliable Status of SLAA 1: ELAA is reliable 0: ELAA is not reliable Reliability signal: 1: All values of letter box detection are reliable 0: All values of letter box detection are not reliable Signals new values for letter box detection 1: new values can be read 0: current letter box detection measurement not finalized ("IC Bus" on page 123)
STATUS_SLAA
STATUS_ELAA
7Bh
RELY
7Bh
LBDSTATUS
7Ch
Table 32
Input read IC Bus parameter
54
Micronas
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Preliminary Data Sheet
System description
5.5
Clock concept
Signals CLKM CLKS X1/CLKD
Pin number 18 58 2
Description System clock input master channel System clock input slave channel System clock input display channel
Table 33
Input signals
Signals CLKOUT
Pin number 3
Description Clock output
Table 34
Output signals
The SDA 9415 supports different clock concepts. The Figure 24 shows a typical application of the SDA 9415. The frontend clock is connected to CLKM input. The second frontend clock is connected to CLKS input. The CLKOUT pin is connected to the backend and the X1/CLKD input is connected to a crystal oscillator. The Figure 23 explains the clock switch, which may be used for the separate modes (see also Table 37 "Ingenious configurations of the HOUT and VOUT generator" on page 84).
CLKS
PLLS
CLKS_pll clock3 CLKOUT
CLKM
PLLM
CLKM_pll
0 X1/CLKD
PLLD
CLKD_pll
1
CLKMDEN
Figure 23
Clock concept of SDA 9415
55
Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
YUVINM
8
Y U CVBS Analog colour decoder V SDA 9206 ABACUS SYNC
Y U
R G B
HINM VINM CLKM = 27 MHz
V
SDA 9380 SDA 9415 Y U CVBS Analog colour decoder V SDA 9206 ABACUS SYNC YUVINS
8
DAEDALUS
VOUT
Deflection controller + H-Drive RGB processing
HINS
HOUT V-Drive CLKOUT E/W
VINS CLKS = 27 MHz
Figure 24
Application for SDA 9415
CLKMDEN (5Fh) 0 1
PLLD input CLKM X1/CLKD
Clock CLKM_pll CLKS_pll CLKD_pll
Used in block ISCM, IFCM, VHCOMM, TSNR, LBD, LM, IC ISCS, IFCS, VHCOMS, LM, IC OSCM/S, ME, SRCM, SRCS, ED, MC, LM, DLTI, DCTI, Peaking, DAC, IC
Table 35
Clock concept switching matrix
56
APPLIK01
Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
IC Bus parameter PLLMOFF 1: off 0: on PLLMRA PLLSOFF 1: off 0: on PLLSRA PLLDOFF 1: off 0: on PLLDRA CLKOUTON 1: enabled 0: disabled CLKMDEN 1: X1/CLKD 0: CLKM
Sub address 00h
Description PLLM master channel on or off, only for test purpose
00h 22h
PLLM range, only for test purpose PLLS slave channel on or off, only for test purpose
22h 5Fh
PLLS range PLLD display channel on or off, only for test purpose
5Fh 5Fh
PLLD range Output of system clock CLKOUT
5Fh
Input clock for PLLD
Table 36
Input write IC Bus parameter
5.6 5.6.1
Application modes and memory concept Introduction
The Main Memory of the SDA 9415 has an overall capacity of 6 Mbit. It is divided into two identical and independent 3 Mbit parts. The Main Memory has 2 completely independent data inputs (master and slave channel) to enable a multitude of PIP features. In general the channels are asynchronous having 2 separate clock PLLs (CLKM, CLKS). Reading of master and slave data for display is performed using a third asynchronous clock (CLKD). In this way a decoupling of input and output clocks is achieved. The Main Memory supports different operation modes of the SDA 9415 by adapted data configurations. The different modes are defined by the IC Bus parameter MEMOP (IC Bus sub address 53h).
57
Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
MEMOP 00 01 10 11
Memory operation mode SRC-Mode (Sample Rate Conversion) SSC-Mode (Split screen) MUP-Mode (Multi picture) not defined
Table 37
Definition of MEMOP
In SRC operation mode the capacity to store 2 fields of the luminance and chrominance components of the master channel is supplied (4:1:1 or 4:2:0 format, IC Bus parameter CHRFORM/CHRFORS, 12h/34h).
CHRFORM 00 01 1X
Data format 4:1:1 4:2:0 reserved
CHRFORS 0 1
Data format 4:1:1 4:2:0
Table 38
Definition of CHRFORM/CHRFORS
The Figure 25 shows the differences between the 4:1:1, 4:2:2 and 4:2:0 data format.
58
Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
4:2:2 1. line
Y0 U0 V0 Y1 Y2 U2 V2 Y3 Y4 U4 V4 Y5 Y6 U6 V6 Y7 Y0 Y1 U0 V0
4:1:1
Y2 Y3 Y4 Y5 U4 V4 Y6 Y7 Y0 U0 V0 Y1
4:2:0
Y2 U2 V2 Y3 Y4 U4 V4 Y5 Y6 U6 V6 Y7
2. line
Y0 U0 V0
Y1
Y2 U2 V2
Y3
Y4 U4 V4
Y5
Y6 U6 V6
Y7
Y0
Y1 U0 V0
Y2
Y3
Y4
Y5 U4 V4
Y6
Y7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
3. line
Y0 U0 V0
Y1
Y2 U2 V2
Y3
Y4 U4 V4
Y5
Y6 U6 V6
Y7
Y0
Y1 U0 V0
Y2
Y3
Y4
Y5 U4 V4
Y6
Y7
Y0 U0 V0
Y1
Y2 U2 V2
Y3
Y4 U4 V4
Y5
Y6 U6 V6
Y7
dataform
Figure 25
Supported data formats
Additionally 3 fields of a decimated picture of the slave channel with the size of up to 1/ 9 of the original format can be stored (4:1:1 or 4:2:0 format). In this mode motion estimation and compensation (Micronas VDU algorithm) for the master channel is supported (up to 30 MHz clock frequency). In parallel it is possible to insert the slave channel at any display position using frame mode and without joint lines. Noise reduction algorithm by recursive filtering is supported only for the master channel in SRC-Mode. In SSC-Mode the data configuration of master and slave channel can be different. Depending on the picture size it is possible to store only 1 field of luminance and chrominance data or 2 fields. The data configuration can be defined by the IC Bus parameters ORGMEMM and ORGMEMS, respectively.
ORGMEMM 1 0
Data configuration of the memory 2 fields (limited picture size in SSC- and MUP-Mode) 1 field
Table 39
Definition of ORGMEM
ORGMEMS 1 0
Data configuration of the memory 3 fields PIP (SRC-Mode), 2 fields (restricted picture size, SSC and MUP Mode) Slave channel blocked (SRC-Mode and ORGMEMM=1) 1 field (SSC- and MUP-Mode; SRC-Mode and ORGMEMM=0)
Table 40
59
Definition of ORGMEMS
Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description Having 2 fields available for the master channel joint line free display can be activated. Storing 2 fields for both channels a complete joint line free display is possible. In both cases a suitable shift of the output raster phase is necessary (especially for 'Double Window' / 'Split Screen' / 'Picture And Picture' / 'Side by Side'). In SSC mode field repetition (Simple 100Hz AABB; Field repetition AAAA or BBBB) is used for interlaced scan (100/120 Hz) rate conversion, ABAB modes are not supported. For progressive scan conversion also only field based algorithms are possible (Simple 50Hz AA*, B*B; Field repetition AA*, B*B). For the definition of the different scan rate conversion algorithms compare "Operation mode generator" on page 87. Positioning of the pictures on the display is done externally by specifying the start of reading for both channels. In MUP-Mode the configurations and functions for both channels are programmable independently. Two fields of the master channel can be stored to achieve a joint line free display of one decimated live picture. Applying smaller decimation factors only one field can be stored and joint line free display is not possible any more. These 2 modes correspond to SSC configuration for the master channel, AABB mode is supported. For the second channel or for both channels any number of decimated fields can be stored step by step. The horizontal positions of the pictures are adjustable in steps of 4 pixel, the vertical positions are also variable and have a step size of 2 lines. The width and the height of a decimated picture depend on the corresponding decimation factors. A maximum of 1 picture per channel can be live. Only field repetition (AAAA, BBBB) is supported in this mode. Other display modes cause raster artefacts in live pictures. Joint lines are also not removed in live pictures. A special MUP-Mode based on SSC memory configuration enables storing of 2 fields of a decimated still picture. The fields are calculated using only one input field for decimation. The generated lines are interpreted alternating as A- and B-lines. The described method improves vertical resolution of still pictures clearly without causing motion artefacts. The limited memory capacity does not allow to fill the complete display with decimated pictures created with the described method using only one channel. The different configuration can be selected by the IC Bus parameter VERRESM and VERRESS, respectively.
VERRESM/VERRESS 1 0
Vertical resolution in MUP-Mode (ORGMEMM/ORGMEMS=1 and WRFLDM/WRFLDS=1) frame resolution field resolution
Table 41
Definition of VERRESM/VERRESS
60
Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
5.6.2
Configuration controlling
The following Table 42 and Table 43 summarize all possible combinations of memory data configurations for the master and slave channel and the corresponding applications. The main configurations are no. 1 for motion compensated up conversion and PIP insertion, no. 5 for joint line free Split Screen display and no. 9 for high quality Multi Picture including one live channel. Table 44 shows the possible picture sizes. The data formats can be always 4:2:0 or 4:1:1. In SSC and MUP mode the picture sizes are influenced by the IC Bus parameters MEMWRM and MEMWRS.
Config.
MEMOP
ORGMEMM
ORGMEMS
Master Channel Fields Y C 2 2 1 1 2 2 1 1 2 2 1 1
Slave Channel Fields Y 3 C 3
1 2 3 4 5 6 7 8 9 10 11 12
00 00 00 00 01 01 01 01 10 10 10 10
1 1 0 0 1 1 0 0 1 1 0 0
1 0 1 0 1 0 1 0 1 0 1 0
2 2 1 1 2 2 1 1 2 2 1 1
not available 3 2 1 2 1 2 1 2 1 2 1 3 2 1 2 1 2 1 2 1 2 1
Table 42
Programmable data configurations
61
Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
Config. 1 2 3
Mode SRC SRC SRC
Application motion compensated up conversion (4:1:1 or 4:2:0) + PIP (ABAB, frame based) motion compensated up conversion with enlarged picture size, no PIP facility AABB conversion for master and slave channel, slave data is written twice (PIPand SSC-configuration) used during switching from configuration 1 to configuration 7 without artefacts 2 independent not synchronized full size channels, AABB conversion joint line free 'Double Window' / 'Split Screen' / 'PAP' display, AABB conversion display of 2 live channels, AABB conversion slave channel exceeds the maximum double window size display of 2 live channels, AABB conversion master channel exceeds the maximum double window size 2 independent not synchronized full size channels, AABB conversion high resolution Multi Picture for master and slave channel (one live picture possible) AABB conversion high resolution Multi Picture for master channel, reduced resolution Multi Picture for slave channel, AABB conversion reduced resolution Multi Picture for master channel, high resolution Multi Picture for slave channel, AABB conversion reduced resolution Multi Picture for master and slave channel, AABB conversion
4 5 6 7 8 9 10 11 12
SRC SSC SSC SSC SSC MUP MUP MUP MUP
Table 43
Applications of different data configurations
62
Micronas
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Preliminary Data Sheet
System description
Config.
Master Channel Size [Pixel X Lines] MEMWRM=0 MEMWRM=1
Slave Channel Size [Pixel X Lines] MEMWRS=0 256 X 104 not available 256 X 104 / 512 X 176 768 X 341 768 X 170 768 X 170 768 X 341 768 X 341 768 X 170 768 X 170 768 X 341 768 X 341 512 X 256 512 X 512 512 X 256 512 X 512 512 X 256 512 X 512 512 X 256 512 X 512 768 X 170 768 X 341 768 X 170 768 X 341 768 X 170 768 X 341 768 X 170 768 X 341 MEMWRS=1
1 2 3 4 5 6 7 8 9 10 11 12
768 X 288 768 X 341 768 X 288 768 X 341 512 X 256 512 X 256 512 X 512 512 X 512 512 X 256 512 X 256 512 X 512 512 X 512
Table 44
Maximum picture sizes
MEMWRS 1 0
Memory write mode slave channel max. 768 pixel/line max. 512 pixel/line
Table 45
Definition of MEMWRS
MEMWRM 1 0
Memory write mode master channel (ORGMEM=01 or 10, SSC or MUP Mode) max. 768 pixel/line max. 512 pixel/line
Table 46
Definition of MEMWRM
63
Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
IC Bus parameter [Default] CHRFORM [0) CHRFORS [0] ORGMEMM [1] ORGMEMS [1] MEMOP [00] VERRESM [0] VERRESS [0] MEMWRM [0] MEMWRS [0]
Sub address
Description
12h 34h 58h 57h 53h 58h 57h 58h 57h
Chrominance data format master channel Chrominance data format slave channel Data configuration of the memory master channel Data configuration of the memory slave channel Memory operation mode Vertical resolution master channel Vertical resolution slave channel Memory write mode master channel Memory write mode slave channel
Table 47
Input write IC Bus parameter
5.6.3
SRC mode configuration
Conditions:MEMOP=00, ORGMEMM=1, ORGMEMS=1 The described data configuration is typical for normal SRC mode with motion compensated 100 Hz ABAB conversion and joint line free frame based PIP insertion.
maximum picture size (master Channel) : 768 pixel X 288 lines
maximum picture size (slave channel) : 256 pixel X 104 lines
5.6.4
SSC and MUP mode configuration
Conditions: MEMOP=01 or 10, ORGMEMM=1, ORGMEMS=1
64
Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description This is the typical configuration needed for joint line free 'Split Screen' / 'Double Window' or 'PAP' display in 4:1:1 or 4:2:0 format using AABB conversion. The same configuration can be used for Multi Picture mode displaying a joint line free live picture and multiple high resolution still pictures.
maximum picture size (master and slave) : 512 (768) pixel X 256 (170) lines In MUP-Mode it is possible to write only A fields into the memory. Therefore the IC Bus parameters WRFLDM and WRFLDS can be used.
WRFLDM / WRFLDS 1 0
Write field (MUP-Mode, MEMOP=10) only A fields are written all fields are written corresponding to the actual mode
Table 48
Definition of WRFLDM/WRFLDS
IC Bus parameter [Default] WRFLDM [0] WRFLDS [0]
Sub address
Description
58h 57h
Write field master channel (MUP-Mode) Write field slave channel (MUP-Mode)
Table 49
Input write IC Bus parameter
5.6.5
Configuration switch
This chapter deals with the switching between the different operation modes without causing visible picture artifacts. The typical application concerns the transition from SRC-PIP mode to SSC double window mode (see figure 26 on page 67 and figure 27 on page 68) and furthermore to an exchange of master and slave channel (see figure 28 on page 69).
65
Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
ORGMEMM 0 1
Data configuration of the memory (Master Channel) SRC mode, ORGMEMM=1: no slave channel available SRC mode, ORGMEMM=0, SSC- and MUP-mode: 1 field is stored SRC-mode: 3 fields are stored for PIP SSC- and MUP-mode: 2 fields are stored
Table 50
Definition of ORGMEMM
ORGMEMS 0 1
Data configuration of the memory (Slave Channel) SRC mode, ORGMEMM=1: no slave channel available SRC mode, ORGMEMM=0, SSC- and MUP-mode: 1 field is stored SRC-mode: 3 fields are stored for PIP SSC- and MUP-mode: 2 fields are stored
Table 51
Definition of ORGMEMS
MEMRDM 1 0
Memory read mode master channel (SRC-Mode, MEMOP=00) Reading only field memory area for AABB conversion Reading both field memory areas for ABAB conversion
Table 52
Definition of MEMRDM
MEMRDS 1 0
Memory read mode slave channel (SRC-Mode, MEMOP=00) Reading data in PIP-configuration (joint line free, ABAB) Reading data in SSC-configuration, 1 or 2 decimated fields, AABB
Table 53
Definition of MEMRDS
66
Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
MEMWRM 0 1
Memory read mode master channel (only for SSC- and MUP-mode) 512 pixel / line 768 pixel / line
Table 54
Definition of MEMWRM
MEMWRS 0 1
Memory read mode slave channel SRC-mode: writing data in PIP configuration SSC- and MUP-mode: 512 pixel / line SRC-mode: writing data in PIP- and in SSC configuration SSC- and MUP-mode: 768 pixel / line
Table 55
Definition of MEMWRS
A typical animated transition to a double window display can be divided into two parts: changing the operation mode from SRC to SSC (figure 26 on page 67) and changing the picture sizes and positions continuously according to a double window display (figure 27 on page 68). In SSC mode no vector driven up conversion modes are possible. Only field based algorithms are supported. The corresponding IC commands are summarized in Table 56 and Table 57.
M
S
M
S
SRC-PIP Mode, ABAB (A+B)
SSC-Mode, AABB (A+B)
Figure 26
Switching from SRC-PIP mode to SSC mode
67
Micronas
JLC.vsd/10 SwMode1.WMF
SDA 9415 - B13
Preliminary Data Sheet
System description
M
S
M
S
SSC-Mode, AABB (A+B): -master picure becomes smaller -slave picture becomes larger
SSC-Mode: Double Window, AABB (A+B)
Figure 27
Changing picture sizes to get a double window display
Steps MEMOP 1 2 00 00
ORGMEMM 1 1
ORGMEMS 1 1
MEMWRM 0 0
MEMWRS 0 0
MEMRDS 0 0
MEMRDM 0 0
Operation SRC mode with 1/9 PIP insertion a field based up conversion mode must be programmed by STOPMOM and STOPMOS only one field is read for master channel (reduced vertical resolution) memory capacity of master channel is reduced to 1 field memory organization of slave channel is prepared for SSC configuration slave channel reading is switched to SSC memory configuration SSC mode: full size master picture, 1/9 size of slave picture
2a*
00
1
1
0
0
0
1
3
00
0
1
0
1
0
X
4 5
00 01
0 0
1 1
0 1
1 0
1 X
X X
Table 56
Switching from SRC PIP mode to SSC mode
* Step 2a may be left out
68
Micronas
JLC.vsd/10 SwMode2.WMF
SDA 9415 - B13
Preliminary Data Sheet
System description
Steps MEMOP 6 01
ORGMEMM 0
ORGMEMS 1
MEMWRM 1
MEMWRS 0
MEMRDS X
Operation changing picture sizes of master and slave by programming the corresponding decimation IC Bus parameters reducing the width below 512 pixel for the master picture two fields can be stored
7
01
1
1
0
0
X
Table 57
Changing the picture sizes to double window format
Starting in SRC mode with a PIP insertion (step 1) at first a field based up conversion mode must be chosen for both channels, e.g. AABB conversion for interlaced modes and intrafield interpolation for progressive modes (step 2). Now the capacity for the master channel can be reduced to 1 field (step 3). The free memory capacity is used to write the slave data at two address areas in parallel corresponding to SRC-PIP configuration and SSC configuration. In step 4 the reading of the slave channel data is switched to SSC configuration. In the last step also the master channel is switched to SSC mode. In this configuration we can store 1 field of the master channel and 2 fields of the slave channel. The Joint Line Controller can be activated and joint line free display is possible. Reducing the size of the master picture and enlarging the slave picture size is performed in step 6 in table . During this phase we can get problems with joint line free display of the master picture until the horizontal width is below 512 pixel. Now also the master channel is enabled to store 2 fields and joint line free display is possible again (step 7). In this configuration double window display is performed. During all steps positioning of both pictures is free programmable to enable multiple variations of the animation.
M M S
S
JLC.vsd/11 SwMode3.WMF
SSC-Mode, AABB (A+B): -master picure becomes smaller -slave picture becomes larger
SRC-PIP Mode, ABAB (A+B)
Figure 28
Completing the operations to a master slave exchange
69
Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
Steps MEMOP 8 01
ORGMEMM 1
ORGMEMS 1
MEMWRM 0
MEMWRS 0
MEMRDS X
Operation changing picture sizes of master and slave by programming the corresponding decimation IC Bus parameters exceeding a width of 512 pixel for the slave picture only one field can be stored further changes of picture sizes until full size slave picture and 1/9 size master picture is displayed switching synchronization to slave channel and exchanging the inputs switching to SRC mode using still field based up conversion slave channel reading is switched to SRC memory configuration also the master channel works frame based programming STOPMOM and STOPMOS to frame based up conversion
9 10
01 01
1 1
0 0
0 0
1 1
X X
11 12 13 14 15
01 00 00 00 00
0 0 0 1 1
1 1 1 1 1
1 0 0 0 0
0 1 1 0 0
X 1 0 0 0
Table 58
Performing a master slave exchange
Starting with the double window configuration (figure 27 on page 68) the procedure is continued with an animation to perform an exchange of the master and slave sources to get a display like it is shown in figure 28 on page 69. In step 8 the picture size of the master channel is decreased and the size of the slave picture is increased continuously. When the width of the slave picture exceeds 512 pixel only one field can be stored (step 9). Joint line free display of the slave channel is not always possible in this configuration. When full size slave picture format and 1/9 master picture size is reached (step 10) an exchange of master and slave channel is possible. Unstable picture phases can be avoided when the display raster phase is adapted to the slave channel before the hardware exchange of both sources is done. For display phase raster shifting see "Master slave switch" on page 72. Now we can activate the SRC mode again. At first we just change the mode maintaining the field based conversions (step 12). Then the slave data configuration of the memory is changed to SRC configuration (step 13) and at last the master channel memory capacity is enlarged to 2 fields (step 14) and frame based up conversion modes are enabled (step 15).
70
Micronas
SDA 9415 - B13
Preliminary Data Sheet
System description
5.6.6
Joint line free display
This chapter describes the IC Bus parameters to get a joint line free display in SSC mode.
IC Bus parameter [Default] RSHFTM [0]
Sub address
Description
55h
Joint line free display of master channel by shifting the output raster phase (SSC-Mode) 1: enabled 0: disabled Joint line free display of master and slave channel by shifting the output raster phase (SSC-Mode, RSHFTM=1) 1: enabled 0: disabled Increment for raster phase shift per output frame (lines) Threshold to display progressive PIP without joint lines
RSHFTS [0]
55h
SHFTSTEP [0100]
PROG_THRES [0111100]
55h 56h
Table 59
Input write IC Bus parameter
IC Bus parameter SHIFTACT
Description indicates active shifting process of the display raster phase 0: display phase shifting not active 1: display phase shift active
Table 60
Output read IC Bus parameter
A special circuit is implemented to achieve a joint line free display in SSC mode (e.g. Double Window Display). This circuit synchronizes the two input sources and removes the joint lines by automatic controlled shifting of the display raster phase. This procedure enlarges the value of OPDELM resulting in an delayed start of the output processing. The IC Bus parameters RSHFTM and RSHFTS enable joint line free display for master and slave channel, separately. SHFTSTEP fixes the amount of lines which is added to OPDELM with each output frame. The readable IC Bus parameter SHIFTACT signalizes the progressing shifting operation. It is recommended to enable the registers RSHFTM and RSHFTS in all application modes.
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Preliminary Data Sheet
System description
Mode
Input Master Channel 625/50i 525/60i 625/50i 525/60i 625/50i 525/60i 625/50i 525/60i
Input Slave Channel 625/50i 525/60i 525/60i 625/50i 625/50i 525/60i 525/60i 625/50i
Output Display Channel 625/100i 625/50p 525/120i 525/60p 625/100i 625/50p 525/120i 525/60p 625/100i 625/50p 525/120i 525/60p 625/100i 625/50p 525/120i 525/60p
Comment
SRC SRC SRC SRC SSC/ MUP SSC/ MUP SSC/ MUP SSC/ MUP
Motion compensation for master channel possible Motion compensation for master channel possible joint line free display for slave channel possible (NEW) joint line free display for slave channel possible (NEW) No motion compensation possible No motion compensation possible No motion compensation possible, no joint line free display for slave channel possible No motion compensation possible, no joint line free display for slave channel possible
Table 61
Supported data formats
5.6.7
Master slave switch
This chapter describes the IC Bus parameters used to execute a master and slave exchange.
IC Bus parameter [Default] MASTSLA [0] Sub address Description
55h
Master / Slave shift: 1: Master and slave input signals are exchanged, reset of display raster shift 0: Display raster is synchronized to input master channel (vertical sync) Master / Slave shift: 1: Display raster is shifted slave phase to prepare a master/slave switch 0: Display raster is synchronized to input master channel (vertical sync)
MASLSHFT [0]
56h
Table 62
Input write IC Bus parameter
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Preliminary Data Sheet
System description
IC Bus parameter [Default] SHIFTACT
Sub address
Description
7Fh
Shifting of display raster phase active 1: phase shift in progress 0: phase shift not active
Table 63
Output read IC Bus parameter
Master slave exchange means an animated exchange of the master and slave picture source without visible synchronization problems of the deflection PLL compared with a hard switch between both sources. To avoid this synchronization problem the display raster phase is slowly shifted to a position that fits to the slave channel sync pulses. Then the exchange can be done without visible artefacts. For the animation see "Configuration switch" on page 65. What to do to perform a master slave switch: 1.IC Parameter MASLSHFT must be set. Shift process is started. 2.The IC output signal SHIFTACT must be observed. After setting MASLSHFT is becomes '1' and signalizes that the shift process is active. When it becomes '0' the shift process is finished and the desired phase of the display raster is obtained. 3.At the same time exchanging of master and slave inputs and setting of IC parameter MASTSLA must be performed. Now the chip is synchronized to the former slave channel that now has become the master. 4.At last the IC Bus parameters MASLSHFT and MASTSLA should be reset.
5.6.8
Refresh and still picture mode
The master and the slave channel picture can be frozen by the IC Bus parameter FREEZEM and FREEZES, respectively. The IC Bus parameters REFRON and REFRPER may be used to activate a memory refresh for the internal memory.
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Preliminary Data Sheet
System description
IC Bus parameter [Default] FREEZEM [0] FREEZES [0] REFRPER [00]
Sub address
Description
58h
Freeze picture master 1: freezed (no writing of master channel) 0: live Freeze picture slave 1: freezed (no writing of slave channel) 0: live Refresh period of the memory (REFRON=1; 50 Hz, 625 lines standard) 00: ~ 10ms 01: ~ 7ms 10: ~ 5.5ms 11: ~ 4ms Refresh of internal memory 1: memory refresh activated 0: no memory refresh
57h
53h
REFRON [0]
55h
Table 64
Input write IC Bus parameter
5.6.9
Memory management and animation controlling
The "Example for animation" on page 75 shows a possible application of the SDA 9415. 11 still pictures plus one life picture (cup of coffee) are located around a second life (boat) picture (see picture number 1). The still pictures plus one life picture (cup of coffee) are located in the slave memory and the life picture (boat) in the master memory. The user wants to switch now between the cup of coffee and the boat channel. A possible animation could look like this. The boat will be compressed and disappears (number 2 and number 3). Due to the fact, that only background colour should be visible, the parts of the life picture, which disappear after compression, will be overwritten with the back ground colour. Afterwards the new channel is expanded and overwrites the border colour (cup of coffee, number 4 and number 5). To support this and other features several IC Bus parameters exists, which will be described in more detail afterwards.
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Preliminary Data Sheet
System description
Still picture Life picture
1
2 3
5
Life picture
4
Figure 29
Example for animation
The IC Bus parameters IPOSXM and IPOSYM or IPOSXS and IPOSYS, respectively, specify the position of the left upper corner of a stored picture. The figure below explains the functionality of the IC Bus parameters. The whole memory is organized as blocks, which have a width of 32 pixels. The position (x,y) defined by the IC Bus parameters is defined by the equation below:
x, y = ae 32
Figure 30
* ae IPOSXMo + 4 * IPOSXM -----------------------8
modulo 8 , IPOSYMo
Equation of the position of the left upper picture corner
The IPOSYM and IPOSYS IC Bus parameter specify the vertical position with a resolution of one line for 4:1:1 format and 2 lines for 4:2:0 format for the master and slave channel, respectively. The 5 MSBs of the IPOSXM and IPOSXS defines the horizontal position with a resolution of 32 pixels (block resolution). The 3 LSBs of IPOSXM and IPOSXS are used for fine positioning of the picture in a block with a resolution of 4 pixels. Due to the fact, that only blocks can be written to the memory, the pixels left of the fine positioning are filled up with border values (border values are defined by YBORDERM/ YBORDERS, UBORDERM/UBORDERS, VBORDERM/VBORDERS). If the number of pixels is smaller as 32 pixels (block size), the missing pixels of a block are also filled up with border values.
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Preliminary Data Sheet
System description
32 * (IPOSXM)/8 32 64 0
IPOSYM 0 1 2 3 4
x/pixels
block
y/lines 0 4 8 24 28 32
4 * (IPOSXM modulo 8)
Figure 31
Explanation of memory management I
The Figure 32 shows a picture (boat, number 1), which is located with the left upper corner at the position (x1,y1). The picture will be compressed in vertical and horizontal direction and stored at the position (x2,y2). The vertical and horizontal compression mechanism of the input signal was explained before (compare "Vertical and horizontal compression (VHCOMM/VHCOMS)" on page 36). This result could look like as showed in the picture number 2b. Parts of the original boat are still visible. Therefore in addition the IC Bus parameters LEBORDM/LEBORDS, RIBORDM/RIBORDS, UPBORDM/UPBORDS and LWBORDM/LWBORDS exist. These IC Bus parameters specify the amount of pixels at the left side and the right side and the amount of lines at the top and the bottom which has to be written in addition into the memory with coloured border values (IC Bus parameters YBORDERM, YBORDERS, UBORDERM, UBORDERS, VBORDERM, VBORDERS). Then the result could look like as showed in the picture number 2a (white border colour). The amount of pixels at the left side can be defined by the IC Bus parameters LEBORDM/LEBORDS (amount of border pixels = 4 * LEBORDM/LEBORDS) and the amount of pixels at the right side can be defined by the IC Bus parameter RIBORDM/RIBORDS (amount of border pixels = 4 * RIBORDM/ RIBORDS). The maximum amount of pixels, which can be written in addition, is 28 pixels on each side. The IC Bus parameters UPBORDM/S and LWBORDM/S specify the amount of lines which has to be written in addition into the memory at the upper and lower edge of the picture with coloured border values. The maximum amount of lines, which can be written in addition, is 15 on each side. But there is a limitation that the sum of UPBORDM/UPBORDS + LWBORDM/LWBORDS should not exceed 20 (PAL) lines. In horizontal direction as mentioned before only blocks (32 pixels) can be written into the memory. That means for instance if the LEBORDM parameter has a value bigger as zero and the 3 LSBs of IPOSXM parameter are zero (start position at a begin of a block), that the complete block on the left side of the block specified by IPOSXM will be filled with border colour.
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Preliminary Data Sheet
System description
(X1,Y1) (X2,Y2) LEBORDM RIBORDM
UPBORDM
1
x = 32 * IPOSXM/8 + 4 * (IPOSXM modulo 8)
2a
LWBORDM
2b
Figure 32 Explanation of memory management II So the animation shown in the Figure 32 can be done in the following way. The picture (boat) has at the beginning a defined size (defined by the IC Bus parameters APPLM1, ALPFM1, INTHM1, DEZHM1, INTVM1, DEZVM1) and the left upper corner of the picture is located at the position (x1,y1) (defined by IPOSXM1, IPOSYM1). Specify the new picture size. Set the corresponding IC Bus parameters (APPLM2, ALPFM2, INTHM2, DEZHM2, INTVM2, DEZVM2) to get the new picture size. Specify the new vertical and horizontal position (x2,y2) (defined by IPOSXM2, IPOSYM2). Specify in addition the amount of lines at the upper and lower edge, which has to be overwritten with border values. In addition the amount of pixels at the left and right edge, which has to be overwritten with border values (LWBORDM, UPBORDM, LEBORDM, RIBORDM). Send the new values to the IC interface. Remember that the reduction of the picture is limited in horizontal and vertical direction, if the border should be overwritten with border colour. The Figure 33 shows in detail what happens by means of a horizontal bar, which is horizontally reduced. The width of the bar is 84 pixels (compare Figure 33). The position x1, defined by IPOSX1 is for instance, IPOSXM1=00001100b=12 => x1 = 32 * 1 + 4 * 4 = 48 The IC Bus parameters LEBORDM and RIBORDM are both equal 0. The first block and the last block are filled up with border values (black colour - background value). The bar is compressed horizontally and the new width of the bar is 44 pixels. The new position defined by IPOSX2 after the reduction step may be IPOSXM2=00010001b=17=>x2 = 32 * 2 + 4 * 1 = 68. That means the actual picture size is reduced for 40 pixels, 20 pixels at the left side (Left Side = 68 - 48 = 20) and 20 pixels at the right side (Right Side = 132 - 20). Therefore the
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Preliminary Data Sheet
System description IC Bus parameter LEBORDM has to be set to LEBORDM=5 (amount of pixels = 4*LEBORDM = 4*5 = 20), if the pixels remaining in the memory should be overwritten with border values. In addition the IC Bus parameter RIBORDM has to be set to RIBORDM=5 (amount of pixels = 4*RIBORDM = 4*5 = 20), if the pixels remaining in the memory should be overwritten with border values. The new position of the left edge is 68 and begin of the block is 64, thus the difference between the begin of the bar and the actual block is 68-64=4. That means that from the additional 20 pixels, which have to be written left of the bar, at least 16 pixels belong to the block which begins at the position 32. That means, that the complete block (begin at position 32) is filled up with border values. The same argumentation is valid for the right edge of the bar.
32 * (IPOSXM)/8 32 64 96 128
48 132
0 IPOSYM 0 1 2
pixels
0 IPOSYM 0 1 2
32 * (IPOSXM)/8 32 64 96 128
68 112
pixels
Reduction
vhcomba3
lines
lines
1
APPLM1 = 21 -> 8*21/2 = 84 pixel IPOSX1 = 00001100=12 x1= 32*1 + 4*4 = 48 LEBORD1 = 0 RIBORD1 = 0 Reduction 40 pixels IPOSX2 = 00010001 x2 = 32*2 + 4*1 = 68 LEBORD2 = 5 RIBORD2 = 5
2
APPLM2 = 11 -> 8*11/2 = 44 pixel
Figure 33
Explanation of memory management III
Repeating the procedure described above must be used for an animation as explained in Figure 29.
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Preliminary Data Sheet
System description
IC Bus parameter [Default] UPBORDM [0] LWBORDM [0] LEBORDM [0] RIBORDM [0] UPBORDS [0] LWBORDS [0] LEBORDS [0] RIBORDS [0] IPOSXM [0] IPOSXS [0] IPOSYM [0] IPOSYS [0]
Sub address
Description
06h 06h 03h 03h 28h 28h 25h 25h 02h 24h 01h 23h
Amount of upper border lines by vertical compression master Amount of lower border lines by vertical compression master Amount of left border pixels by horizontal compression master Amount of right border pixels by horizontal compression master Amount of upper border lines by vertical compression slave Amount of lower border lines by vertical compression slave Amount of left border pixels by horizontal compression slave Amount of right border pixels by horizontal compression slave Horizontal picture position in the memory for master Horizontal picture position in the memory for slave Vertical Picture Position in the Memory for master Vertical Picture Position in the Memory for slave
Table 65
Input write IC Bus parameter
It is possible to write border colours instead of the master or slave channel in different areas. Therefore the IC parameters FORCOLM and FORCOLS can be used.
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Preliminary Data Sheet
System description
IC Bus parameter [Default] YBORDERM [0001] UBORDERM [1000] VBORDERM [1000] YBORDERS [0001]
Sub address
Description
04h
Y border value (Yborder(3) Yborder(2) Yborder(1) Yborder(0) 0 0 0 0 = 00010000 = 16), YBORDERM defines the 4 MSB's of a 8 bit value U border value (Uborder(3) Uborder(2) Uborder(1) Uborder(0) 0 0 0 0 = 10000000 = 128), UBORDERM defines the 4 MSB's of a 8 bit value V border value (Vborder(3) Vborder(2) Vborder(1) Vborder(0) 0 0 0 0 = 10000000 = 128), VBORDERM defines the 4 MSB's of a 8 bit value Y border value (Yborder(3) Yborder(2) Yborder(1) Yborder(0) 0 0 0 0 = 00010000 = 16), YBORDERS defines the 4 MSB's of a 8 bit value U border value (Uborder(3) Uborder(2) Uborder(1) Uborder(0) 0 0 0 0 = 10000000 = 128), UBORDERS defines the 4 MSB's of a 8 bit value V border value (Vborder(3) Vborder(2) Vborder(1) Vborder(0) 0 0 0 0 = 10000000 = 128), VBORDERS defines the 4 MSB's of a 8 bit value Force colour master channel 1: on 0: off Force colour slave channel 1: on 0: off
05h
05h
26h
UBORDERS [1000] VBORDERS [1000] FORCOLM [0] FORCOLS [0]
27h
27h
04h
26h
Table 66
Input write IC Bus parameter
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Preliminary Data Sheet
5.7
Output sync controller (OSCM/S)
Signals HOUT VOUT BLANK
Pin number 4 5 7
Description horizontal synchronization signal (polarity programmable, IC Bus parameter 4Ah HOUTPOL, default: high active) vertical synchronization signal (polarity programmable, IC Bus parameter 4Ah VOUTPOL, default: high active) free programmable horizontal blanking signal (polarity programmable, IC Bus parameter 49h BLANKPOL, default: high active) interlaced signal (can be used for AC coupled deflection circuits)
INTERLACED
6
Table 67
Output signals
The output sync controller generates horizontal and vertical synchronization signals for the scan rate converted output signal. The figure below shows the block diagram of the OSCM/S and the existing IC Bus parameters.
HOUTPOL, HOUTFR, APPLOPD, NAPOPD, BLANLEN, PPLOP, RMODE, BLANDEL, HORPOSM, HORPOSS, HORWIDTHM, HORWIDTHS, HOUTDEL HOUT BLANK VOUT INTERLACED osc01
HIN VIN GMOTION, MOVMO, MOVPH, MOVTYP
OPERATION mode generator
HOUT generator
VOUT generator
STOPMOM, STOPMOS, VOUTPOL, VOUTFR, NALOPD, ALPFOPD, ADOPMOM LPFOP, VERPOSM, VERPOSS, VERWIDTHM, VERWIDTHS, INTMODE
Figure 34
Block diagram of OSCM/S
Furthermore the output sync controller derives framing signals from the generated HOUT and VOUT for the output data processing. The framing signals depend on different IC Bus parameters. The whole output picture is a combination of three channels:
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Preliminary Data Sheet
1: Background channel 2: Output channel master 3: Output channel slave The background channel has always the lowest priority. The priority between output channel master and slave is defined by an IC Bus parameter PRIORMS. The figure below shows an example for the combination of the three channels. The background colour black has lowest priority. The picture content of master channel is a phone and the picture content of slave channel is a airplane. In this case the slave channel has the highest priority. To enable or disable the display of the master or slave channel the IC parameters MASTERON and SLAVEON can be used.
HOUT VOUT (PPLOP*2)*CLKD
(NALOPD+1)*2 VERPOSM
VERPOSS VERWIDTHS*4
4*LPFOP+1
ALPFOPD*8
VERWIDTHM*8
(HORWIDTHM*8)*CLKD (HORPOSM*4)*CLKD (HORPOSS*4)*CLKD (HORWIDTHS*4)*CLKD (APPLOPD*8)*CLKD
(NAPOPD*4)*CLKD
BLANK
(BLANLEN*8)*CLKD ((6 MSBs of BLANDEL)*8 + (2 LSBs of BLANDEL))*CLKD
Figure 35
Output IC Bus parameter
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Preliminary Data Sheet
IC Bus parameter [Default value] NALOPD [22] ALPFOPD [144] VERPOSM [0] VERWIDTHM [72] VERPOSS [0] VERWIDTHS [144] LPFOP [156] NAPOPD [0] APPLOPD [90] HORPOSM [0] HORWIDTHM [90] HORPOSS [0] HORWIDTHS [180] PPLOP [432] BLANDEL [0] BLANLEN [180] HOUTDEL [0] PRIORMS [1]
Sub address 36h 37h 3Ch
Description Not Active Line OutPut Display defines the number of lines from the V-Sync to the first active line of the output frame Active Lines Per Field OutPut Display defines the number of active lines per output frame VERtical POSition Master defines the number of lines from the first active line of the background channel to the first active line of the master channel VERtical WIDTH Master defines the number of active lines of the master channel per output frame VERtical POSition Slave defines the number of lines from the first active line of the background channel to the first active line of the slave channel VERtical WIDTH Slave defines the number of active lines of the slave channel per output frame Lines Per Frame OutPut defines the number of lines per output frame (only valid for VOUTFR=1) Not Active Pixel OutPut Display defines the number of pixels from the H-Sync to the first active pixel Active Pixels Per Line OutPut Display defines the number of pixels per line (background, master and slave channel) HORizontal POSition Master defines the number of pixels from the first active pixel of the background channel to the first active pixel of the master channel HORizontal WIDTH Master defines the number of active pixels of the master channel HORizontal POSition Slave defines the number of pixels from the first active pixel of the background channel to the first active pixel of the slave channel HORizontal WIDTH Slave defines the number of active pixels of the slave channel Pixel Per Line OutPut defines the number of pixels between two consecutive H-Syncs (only valid for HOUTFR=1) BLANk DELay defines the distance from the H-Sync to the active edge of the BLANK signal in number of CLKD clocks BLANk LENgth defines the length of the BLANK signal in number of CLKD clocks Horizontal delay of HOUT and VOUT signal in clocks of CLKD Priority of master or slave channel: 1: master channel priority 0: slave channel priority (SFCPR should be fixed to VSS).
40h 3Dh
41h 38h 39h 43h 3Ah
3Eh 3Bh
3Fh 45h, 46h 42h 44h 35h 43h
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Preliminary Data Sheet
IC Bus parameter [Default value] MASTERON [1] SLAVEON [0]
Sub address 53h
Description Display of master channel: 1: enabled 0: disabled Display of slave channel: 1: enabled 0: disabled
53h
Figure 36
Output write IC Bus parameter
The next paragraphs describe the HOUT and VOUT generator in more detail. Both generators have a so called "locked-mode" and "freerunning-mode". Not all combinations of the modi make sense. The table below shows ingenious configurations.
Mode "H-and-V-locked" "H-freerunning-V-locked" "H-and-V-freerunning"
HOUTFR 0 1 1
VOUTFR 0 0 1
CLKMDEN 0 1 1
Figure 37
Ingenious configurations of the HOUT and VOUT generator
5.7.1
HOUT generator
The HOUT generator has two operation modes, which can be selected by the IC Bus parameter HOUTFR. The HOUT signal is active high (HOUTPOL=0) for 64 clock cycles (X1/CLKD). In the freerunning-mode the HOUT signal is generated depending on the PPLOP IC Bus parameter. In the locked-mode the HOUT signal is locked on the incoming H-Sync signal HIN. The polarity of the HOUT signal is programmable by the IC Bus parameter HOUTPOL. The BLANK signal can be used to mark the active part of a line. To avoid transition artifacts of digital filters the number of active pixels can be symmetrically reduced using the CAPPM and CAPPS IC Bus parameter.
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Preliminary Data Sheet
IC Bus parameter HOUTFR 1: free run 0: locked mode CAPPM 00: k = 0 01: k = 8 10: k = 16 11: k = 24 CAPPS 00: k = 0 01: k = 8 10: k = 16 11: k = 24
Sub address 4Ah
Description HOUT generator mode select
46h
Reducing factor for the HORizontal WIDTH Master value of the master channel Number of active pixels per line = 8 * HORWIDTHM - 2*k
46h
Reducing factor for the HORizontal WIDTH Slave value of the master channel Number of active pixels per line = 8 * HORWIDTHM - 2*k
Table 68
Output write IC Bus parameter
5.7.2
VOUT generator
The VOUT generator has two operation modes, which can be selected by the IC Bus parameter VOUTFR. The VOUT signal is active high (VOUTPOL=0) for two output lines. In the freerunning-mode the VOUT signal is generated depending on the LPFOP IC Bus parameter. In the locked-mode the VOUT signal is synchronized by the incoming V-Sync signal VIN (means the internal VIN delayed by the IC Bus parameter OPDELM, compare "Input sync controller (ISCM/ISCS)" on page 26). The RMODE IC Bus parameter (linescanning pattern mode 1: progressive, 0: interlaced) determines the scan rate conversion mode. If RMODE=1, then for each incoming V-sync signal VIN an outgoing V-sync signal VOUT has to be generated (e.g. 50 Hz interlaced to 50 Hz progressive scan rate conversion). If RMODE=0, then during one incoming V-Sync signal, two VOUT pulses have to be generated (e.g. 50 Hz interlaced to 100 Hz interlaced scan rate conversion).
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Preliminary Data Sheet
VIN RMODE=1 VOUT RMODE=0 VOUT
conv
Figure 38
VOUT generation depending on IC Bus parameter RMODE
The polarity of the VOUT signal is programmable by the IC Bus parameter VOUTPOL. The VOUT signal has a delay of two CLKOUT clocks to the HOUT signal or in case of interlaced a delay of a half line plus two CLKOUT clocks. The INTERLACED signal can be used for AC-coupled deflections. Depending on the IC Bus parameter INTMODE the value of this signal will be generated. The Table 69 shows the definition of this signal (compare "Operation mode generator" on page 87).
output field phase 0 INTMODE INTMODE(0)
output field phase 1 INTMODE(1)
output field phase 2/0 INTMODE(2)
output field phase 3/1 INTMODE(3)
Table 69
Output write IC Bus parameter INTMODE
IC Bus parameter VOUTFR 1: free run 0: locked mode RMODE 1: progressive 0: interlaced INTMODE
Sub address 4Ah
Description VOUT generator mode select
48h
line-scanning pattern mode
49h
Free programmable INTERLACED signal for AC-coupled deflection stages
Table 70
Output write IC Bus parameter INTMODE
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Preliminary Data Sheet
5.7.3
Switching from H-and-V-freerunning to H-and-V-locked mode
In H-and-V-freerunning mode, generally, the phase of the generated synchronization line-scanning pattern has no correlation to the input line-scanning pattern. A hard switch from the H-and-V-freerunning mode to the H-and-V-locked mode therefore would cause visible synchronization artefacts. To avoid these problems the SDA 9415 enlarges the line and the field lengths of the output sync signals HOUT and VOUT in a defined procedure to enable an invisible synchronization of the freerunning output to the input. For vertical synchronization the maximum synchronization time is 260 ms for interlaced and 520 ms for progressive display modes. Horizontal synchronization is performed in a maximum time of 50 ms. To get the best performance it is recommended to change at first the vertical and after the mentioned delay times the horizontal mode from free running to locked.
5.7.4
Operation mode generator
The VOUT generator determines the VOUT signal. For proper operation of the VOUT generator information about the line-scanning pattern sequence is necessary. The IC Bus parameters STOPMOM (STatic OPeration MOde Master), STOPMOS (STatic OPeration MOde Slave) and the IC Bus parameter ADOPMOM (ADaptive OPeration MOde Master) define the line-scanning pattern sequence and the scan rate conversion algorithms.
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Preliminary Data Sheet
FRAME/FIELD
FRAME FIELD A odd lines
FIELD B even lines
Content of picture
DISPLAY LINE-SCANNING PATTERN
TV Display raster odd lines Display line-scanning pattern
even lines
Display line-scanning pattern
Tube, Display raster
Figure 39
Explanation of field and display line-scanning pattern
The interlaced input signal (e.g. 50 Hz PAL or 60 Hz NTSC) is composed of a field A (odd lines) and a field B (even lines). A - Input signal, field A at time n, B - Input signal, field B at time n The field information describes the picture content. The output signal, which could contain different picture contents (e.g. field A, field B) can be displayed with the display line-scanning pattern or . (A ,) - Output signal, field A at time n, displayed as line-scanning pattern (A ,) - Output signal, field A at time n, displayed as line-scanning pattern
n n n n
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Preliminary Data Sheet
((A*) ,) - Output signal, field A line-scanning pattern interpolated into field B at time n, displayed as line-scanning pattern (A B
n n-1
n
,+==Output signal, frame AB at time n, progressive
The table below describes the different scan rate conversion algorithms and the corresponding line-scanning pattern sequences. The delay between the input field and the corresponding output fields depends on the OPDELM parameter and the default value for the delay is an half input field.
time
Fields available in the internal field stores
An-1, Bn-1
Bn-1, An
An, Bn
Output fields
OPDELM lines
cn-1
Phase 2/0
dn-1
Phase 3/1
an
Phase 0
osc02
Input fields
An
Bn
bn
Phase 1
Figure 40
Explanation of operation mode timing
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Preliminary Data Sheet
Input field A STOPMOM 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1100 1101 1110 1111 Scan rate conversion algorithm Output field an phase 0 p(c)*)= p(mc)= p(ma)= An= Bn-1= An= Bn-1= An= An= Bn-1= Bn-1= An= Bn-1= p(ma)= p(mc)= Output field bn phase 1 p(d)= p(md)= p(mb)= Bn-1= An= An= Bn-1= =An= An= Bn-1= Bn-1= (A*)n= (B*)n-1= p(mb)= p(md)=
Input field B Output field cn phase 2/0 p(a)= p(ma)= p(mc)= An= Bn= Bn= An= An= An= Bn= Bn= (B*)n= (A*)n= p(ma)= p(mnc)= Output field dn phase 3/1 p(b)= p(mb)= p(md)= Bn= An= Bn= An= An= An= Bn= Bn= Bn= An= p(mb)= p(mnd)=
VDU, camera mode VDU, film mode, phase 0, PAL VDU, film mode, phase 1, PAL Frame repetition, ABAB FRAME repetition, BABA Simple 100, AABB Simple 100, BBAA Field repetition, AAAA I Field repetition, AAAA II Field repetition, BBBB I Field repetition, BBBB II Simple 100, AA*B*B Simple 100, BB*A*A VDU, film mode, phase 0, NTSC VDU, film mode, phase 1, NTSC
Table 71
Static operation modes (only valid for ADOPMOM=0, RMODE=0)
*)p(a): a field - motion compensated; p(b): b field - motion compensated
p(c): c field - motion compensated; p(d): d field - motion compensated p(ma): a field - motion compensated film mode; p(mb): b field - motion compensated film mode p(mc): c field - motion compensated film mode; p(md): d field - motion compensated film mode p(mnc): c field - motion compensated film mode for NTSC p(mnd): d field - motion compensated film mode for NTSC
90
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Preliminary Data Sheet
Input field A STOPMOM 0000 0001 0010 0011 0100 0101 1100 1101 1110 1111 Scan rate conversion algorithm VDU, camera mode VDU, film mode, phase 0, PAL VDU, film mode, phase 1, PAL Frame repetition, AB Frame repetition, AB median Simple 50, AA*, B*B Field repetition, AA* Field repetion, BB* VDU, film mode, phase 0, NTSC VDU, film mode, phase 1, NTSC Output field phase 0 p(cd)*)= p(mcd)= p(mab)= (A B =
n n-1
Input field B Output field phase 2/0 p(ab)= p(mab)= p(mcd)= (An Bn= ((A*)n Bn= ((B*)n Bn= (An (A*)n= ((B*)n-1 Bn-1= p(mab)= p(mnc)=
(An (B*)n-1= (An (A*)n= (An (A*)n= ((B*)n-1 Bn-1= p(mab)= p(mcd)=
Table 72
Static operation modes (only valid for ADOPMOM=0, RMODE=1)
*)p(ab): a+b field - motion compensated
p(cd): c+d field - motion compensated p(mab): a+b field - motion compensated film mode p(mcd): c+d field - motion compensated film mode p(mnc): c field - motion compensated film mode for NTSC
For STOPMOM=0000 (Micronas VDU) the high performance motion compensation algorithm is used for scan rate conversion which results in a high performance line flicker reduction, double contour elimination and perfect motion display. The table Table 73 "Special combinations of STOPMOM and ADOPMOM" on page 92 explains some important combinations of both registers. It is possible to force some modes like VDU CAMERA, VDU PAL film mode and VDU NTSC film mode with manual or automatic phase detection in case of film mode.
91
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Preliminary Data Sheet
STOPMOM 0000 0001 0010 0001
ADOPMOM 000 000 000 100
Description force VDU CAMERA mode force VDU PAL film mode Phase 0 force VDU PAL film mode Phase 1 force VDU PAL with automatic phase detection; PAL film mode is set only once, if it is detected; after that it will be fixed until another mode is selected from the user; STOPMOM 0001 or 0010 is selected automatically
0010 1110
100 100
same as STOPMOM 0001 and ADOPMOM 100 force VDU NTSC film mode with automatic phase detection; NTSC film mode is set only once, if it is detected; after that it will be fixed until another mode is selected from the user; STOPMOM 1110 and STOPMOM 1111 is selected automatically same as STOPMOM 1110 and ADOPMOM 100 force VDU PAL with automatic phase detection; PAL film mode is set only once, if it is detected; after that it will be fixed until another mode is selected from the user; in addition STOPMOM 0011 will be selected if GMOTION is zero; STOPMOM 0001 or 0010 or 0011 is selected automatically same as STOPMOM 0001 and ADOPMOM 101 force VDU NTSC film mode with automatic phase detection; NTSC film mode is set only once, if it is detected; after that it will be fixed until another mode is selected from the user; in addition STOPMOM 0011 will be selected if GMOTION is zero;STOPMOM 1110 or STOPMOM 1111 or STOPMOM 0011 is selected automatically same as STOPMOM 1110 and ADOPMOM 101
1111 0001
100 101
0010 1110
101 101
1111
101
Table 73
Special combinations of STOPMOM and ADOPMOM
The table Table 74 "Display line-scanning pattern sequence" on page 93 shows all possible display line-scanning pattern sequences for the different static operation modes and the lines per field value between two consecutive output V-Syncs. It is assumed, that in case of freerunning-mode LPFOP=156 and in locked-mode the number of lines of the incoming field is 312.5.
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Preliminary Data Sheet
Display line-scanning pattern sequence
1. to 2. 312 312.5 313 312.5 312 313
2. to 3. 313 312.5 312 312.5 312.5 312.5
3. to 4. 312 312.5 313 312.5 313 312
4. to 5.(1.) 313 312.5 312 312.5 312.5 312.5
Table 74
Display line-scanning pattern sequence
The table below defines the static operation modes for the slave channel. The slave channel is synchronized to the master channel. Therefore only modes with the same output line-scanning pattern as the chosen master channel mode are allowed. Several modes depend on the IC Bus parameter MEMOP.
STOPMOS Scan rate conversion algorithm allowed for RMODE 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 01 SSC 00 SRC 00 SRC all all 01 SSC all allowed output line-scanning pattern = = = = = = = allowed MEMOP 00 SRC 00 SRC all all all all all
000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111
Median, ABAB Frame repetition, ABAB Simple 100, AABB Field repetition, AAAA I Field repetition, AAAA II Field repetition, BBBB I Field repetition, BBBB II not defined Median, AB Frame repetition, AB Line doubling, AB Line doubling, AA Intra field interpolation A+A* Line doubling, BB not defined Intra field interpolation A+A*, B*+B
Table 75
93
Static operation modes slave
Micronas
SDA 9415 - B13
Preliminary Data Sheet
The adaptive operation modes (ADOPMOM) define a dynamic switch between different static operation modes controlled by several internal signals. The start point of all modes is the actual chosen STOPMOM as described before. The tables below shows the different adaptive operation modes. The internal used control signals are GMOTION, MOVTYP, MOVMO and MOVPH (compare "Global motion, film mode and phase detection" on page 108). Furthermore the internal control signal VTSEQ exists. In case of IC Bus parameter VCRMODEM=1, VTSEQ is still zero. If VCRMODEM=0, VTSEQ can be equal one (compare "Input sync controller (ISCM/ISCS)" on page 26). In this cases the scan rate conversion is forced to a simple field based scan rate conversion algorithm. All internal control signals GMOTION, MOVTYP, MOVMO and MOVPH are also readable by the IC Bus interface. Basic adaptive operation modes (RMODE = 0 (interlaced)):
off: ADOPMOM=000/001 MOVMO x MOVPH x MOVTYP x VTSEQM x GMOTION x STOPMOMint STOPMOM STOPMOSint STOPMOS
VCRMODE off: ADOPMOM=010 MOVMO x x MOVPH x x MOVTYP x x VTSEQM 0 1 GMOTION x x STOPMOMint STOPMOM Simple 100, AABB, 0101 STOPMOSint STOPMOS Simple 100, AABB, 010
Still picture mode: ADOPMOM=011 MOVMO x x x MOVPH x x x MOVTYP x x x VTSEQM 0 0 1 GMOTION 0 1 x STOPMOMint Frame repetition, ABAB, 0011 STOPMOM Simple 100, AABB, 0101 STOPMOSint STOPMOS STOPMOS Simple 100, AABB, 010
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Preliminary Data Sheet
Film mode I; ADOPMOM=100 MOVMO 0 1 MOVPH x 0 MOVTYP x 0 VTSEQM 0 0 GMOTION x x STOPMOMint STOPMOM VDU, film mode, phase 0, PAL, 0001 VDU, film mode, phase 1, PAL, 0010 VDU, film mode, phase 0, NTSC, 1110 VDU, film mode, phase 1, NTSC, 1111 Simple 100, AABB, 0101 STOPMOSint STOPMOS STOPMOS
1
1
0
0
x
STOPMOS
1
0
1
0
x
STOPMOS
1
1
1
0
x
STOPMOS
x
x
x
1
x
Simple 100, AABB, 010
Film mode II: ADOPMOM=101 MOVMO x 0 1 MOVPH x x 0 MOVTYP x x 0 VTSEQM 0 0 0 GMOTION 0 1 1 STOPMOMint Frame repetition, ABAB, 0011 STOPMOM VDU, film mode, phase 0, PAL, 0001 VDU, film mode, phase 1, PAL, 0010 VDU, film mode, phase 0, NTSC, 1110 VDU, film mode, phase 1, NTSC, 1111 Simple 100, AABB, 0101 STOPMOSint STOPMOS STOPMOS STOPMOS
1
1
0
0
1
STOPMOS
1
0
1
0
1
STOPMOS
1
1
1
0
1
STOPMOS
x
x
x
1
x
Simple 100, AABB, 010
95
Micronas
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Preliminary Data Sheet
Film mode III: ADOPMOM=110 MOVMO 0 1 MOVPH x 0 MOVTYP x x VTSEQM 0 0 GMOTION x x STOPMOMint STOPMOM VDU, film mode, phase 0, PAL, 0001 VDU, film mode, phase 1, PAL, 0010 Simple 100, AABB, 0101 STOPMOSint STOPMOS STOPMOS
1
1
x
0
x
STOPMOS
x
x
x
1
x
Simple 100, AABB, 010
Film mode IV: ADOPMOM=111 MOVMO x 0 1 MOVPH x x 0 MOVTYP x x x VTSEQM 0 0 0 GMOTION 0 1 1 STOPMOMint Frame repetition, ABAB, 0011 STOPMOM VDU, film mode, phase 0, PAL, 0001 VDU, film mode, phase 1, PAL, 0010 Simple 100, AABB, 0101 STOPMOSint STOPMOS STOPMOS STOPMOS
1
1
x
0
1
STOPMOS
x
x
x
1
x
Simple 100, AABB, 010
Adaptive operation mode (RMODE = 1 (progressive)):
off: ADOPMOM=000/001 MOVMO x MOVPH x MOVTYP x VTSEQM x GMOTION x STOPMOMint STOPMOM STOPMOSint STOPMOS
VCRMODE off: ADOPMOM=010 MOVMO x x MOVPH x x MOVTYP x x VTSEQM 0 1 GMOTION x x STOPMOMint STOPMOM Simple 50, 0101 STOPMOSint STOPMOS Line doubling, AB, 010
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Preliminary Data Sheet
Still picture mode: ADOPMOM=011 MOVMO x x x MOVPH x x x MOVTYP x x x VTSEQM 0 0 1 GMOTION 0 1 x STOPMOMint Frame repetition, ABAB, 0011 STOPMOM Simple 50, 0101 STOPMOSint STOPMOS STOPMOS Line doubling, AB, 010
Film mode I: ADOPMOM=100 MOVMO 0 1 MOVPH x 0 MOVTYP x 0 VTSEQM 0 0 GMOTION x x STOPMOMint STOPMOM VDU, film mode, phase 0, PAL, 0001 VDU, film mode, phase 1, PAL, 0010 VDU, film mode, phase 0, NTSC, 1110 VDU, film mode, phase 1, NTSC, 1111 Simple 50, 0101 STOPMOSint STOPMOS STOPMOS
1
1
0
0
x
STOPMOS
1
0
1
0
x
STOPMOS
1
1
1
0
x
STOPMOS
x
x
x
1
x
Line doubling, AB, 010
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Preliminary Data Sheet
Film mode II: ADOPMOM=101 MOVMO x 0 1 MOVPH x x 0 MOVTYP x x 0 VTSEQM 0 0 0 GMOTION 0 1 1 STOPMOMint Frame repetition, ABAB, 0011 STOPMOM VDU, film mode, phase 0, PAL, 0001 VDU, film mode, phase 1, PAL, 0010 VDU, film mode, phase 0, NTSC, 1110 VDU, film mode, phase 1, NTSC, 1111 Simple 50, 0101 STOPMOSint STOPMOS STOPMOS STOPMOS
1
1
0
0
1
STOPMOS
1
0
1
0
1
STOPMOS
1
1
1
0
1
STOPMOS
x
x
x
1
x
Line doubling, AB, 010
Film mode III: ADOPMOM=110 MOVMO 0 1 MOVPH x 0 MOVTYP x x VTSEQM 0 0 GMOTION x x STOPMOMint STOPMOM VDU, film mode, phase 0, PAL, 0001 VDU, film mode, phase 1, PAL, 0010 Simple 50, 0101 STOPMOSint STOPMOS STOPMOS
1
1
x
0
x
STOPMOS
x
x
x
1
x
Line doubling, AB, 010
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Preliminary Data Sheet
Film mode IV: ADOPMOM=111 MOVMO x 0 1 MOVPH x x 0 MOVTYP x x x VTSEQM 0 0 0 GMOTION 0 1 1 STOPMOMint Frame repetition, ABAB, 0011 STOPMOM VDU, film mode, phase 0, PAL, 0001 VDU, film mode, phase 1, PAL, 0010 Simple 50, 0101 STOPMOSint STOPMOS STOPMOS STOPMOS
1
1
x
0
1
STOPMOS
x
x
x
1
x
Line doubling, AB, 010
Table 76
Adaptive operation modes
Example for explanation of the adaptive operation modes: ADOPMOM = 4: Film mode I, RMODE=0 In this case the scan rate conversion algorithm is controlled by the signal MOVMO, MOVTYP and MOVPH. If MOVMO is equal 0 the scan rate conversion mode is defined by STOPMOM and STOPMOS (e.g. Micronas VDU). If MOVMO is equal 1 and MOVTYP is equal 0 the scan rate conversion algorithm is changed depending on the MOVPH signal to Micronas VDU, Film mode, PAL, phase 0 or 1. If MOVMO is equal 1 and MOVTYP is equal 1 the scan rate conversion algorithm is changed depending on the MOVPH signal to Micronas VDU, Film mode, NTSC, phase 0 or 1. In case of film mode PAL, the MOVPH signal is constant for the applied material. In case of Film mode NTSC, the MOVPH signal changes each 2th or 3th field, respectively.
IC Bus parameter STOPMOM STOPMOS ADOPMOM Table 77
Sub address 48h 4Ah 49h
Description STatic OPeration MOdes Master STatic OPeration MOdes Slave ADaptive OPeration MOdes Master
Output write IC Bus parameter
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Preliminary Data Sheet
5.8
Motion estimation
The 3-D Recursive Search Block-Matching algorithm was introduced as a high performance low-cost motion estimation algorithm suitable for demanding scan rate conversion applications. The figure below explains the principle of the block matching algorithm. The result is a best matching vector, which contains information about velocity and direction of a block at position (x,y).
(vx,vy)T
(x,y)
v (x,y) time T-1
time T
Figure 41 Principle of block matching
The main characteristics of the motion estimator inside of the SDA 9415 are listed in the table below.
IC Bus parameter Horizontal range Vertical range Block size Accuracy Candidates Amount of blocks +/-32 +/-24 8x8 (HxV) +/- 1 8 (2x3 + 2) 90*72 (HXV) pels lines pels (frame grid) pels
Table 78
100
Key IC Bus parameters of the 3-D RS motion estimation
Micronas
me01
SDA 9415 - B13
Preliminary Data Sheet
The Figure 42 shows the block diagram of the motion estimation and motion compensation block. The field information is read line-wise from the internal field store and written to a line-to-block converter. The motion estimation and the motion compensation block read the field information in parallel block wise from the line-to-block converter. The cache in front of the blocks enables a random access of the field information. The result of the motion estimation is stored in the vector memory, which is also used as a vector field memory for the 3-D recursive block matching algorithm. At that time only vector information of block resolution is available. The post processing block computes a vector information of pixel resolution basis, which can be used from the motion compensation block for the up conversion process. Finally the results of the motion compensation block are written to the block-to-line converter block.
Vector memory
BVMRES
Cache Field Store eDRAM Line to Block Converter Cache
Motion Estimation
Vector Post Processing
BVMCON MESMOOTHON
Motion Compensation
ME-IC bus parameter
FILSEL VECDISON
Figure 42
Block diagram of motion estimation and compensation
The Figure 43 illustrates a more detailed block diagram of the motion estimation block. The motion estimation block is separated in two branches. The left one is only responsible for still area detection and the right one for all kind of areas. The additional left branch can be switched off or on by the IC Bus parameter MENULLFUNON (IC Bus parameter 4Bh). Different preprocessing blocks are located in both branches due to the different tasks of the branches. After preprocessing of the input data the main computation, the block matching, is executed. For the right branch, the motion estimator applies two concurrent recursive block matchers, that individually check three candidate vectors with different convergence directions. Among the three candidates there is one spatial prediction vector taken from a previously processed block and a temporal prediction vector. The temporal prediction has the characteristic feature that its position is shifted with respect to the block currently processed in the opposite direction compared to the spatial prediction. The Figure 44
101
me03
Block to Line Converter
Micronas
SDA 9415 - B13
Preliminary Data Sheet
illustrates this feature, and shows that both types of predictions differ for the two estimators (Sa and Ta of the first estimator, Sb and Tb for the second). Both estimators further test one candidate that is found as the sum of their spatial prediction vector and an update vector. The last candidate is the null vector. The left branch contains only a special null block matcher. The best matching null vector from either of the two branches is assigned to the current block. The overall best vector is finally selected and used for scan rate conversion. Different penalty mechanism exist to optimize the behaviour of the both branches of the motion estimation block.
MEVPERTH MEANRG
Pre Processing I
Pre Processing II
MEANMP MEANBP
Block Matching I
Block Matching II
MEADDPEN MEPENUP MENULLPEN MENPTH MEHPERTH MEPERINF PERPEN MENVRTH
MENULLUNFON
Best result
Figure 43
Block diagram of motion estimation
y-Y y y+Y y+2Y Sb
Sa Tb
Convergence direction A current block
Ta block in current field Convergence direction B x-2X x-X x x+X x+2X H-pos block in previous field
Figure 44
Relative positions of the spatial predictors
The IC Bus parameters below are used for optimization purposes of the motion estimation block and should not be changed by the customer.
102
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Preliminary Data Sheet
IC Bus parameter MEANBP MEANMP MEANRG MEHPERTH MEVPERTH MEPERINF BVMRES
Sub address 50h 50h 51h 51h 51h 50h 52h
Description Penalty for border lines in additional null dbd (dbd - displaced block difference) Penalty for middle lines in additional null dbd Range of middle lines in additional null dbd Threshold for horizontal periodicity detection Threshold for vertical periodicity detection Defines influences of periodicity Reset command for block vector memory - Channel switch (on switching to a new channel by remote control, switch on BVMRES once and release; note: reset film mode detection too [RESMOV]) - Freeze picture (on picture freeze switch on BVMRES and hold; alternative: switch to non motion compensated scan rate conversion [STOPMOM/ADOPMOM]) - SSC or MUP mode (on multipicture on double window/split screen display switch on BVMRES and hold) - Switch from SSC/MUP to SRC mode (switch to SRC mode, switch on BVMRES, change master channel display size to full screen [768x576], change back to normal master channel screen size and release BVMRES) - Vector memory reset takes place only on the active master channel output size; to reset the whole vector memory switch to maximum master channel size (768x576) - Minimum hold time for BVMRES to have an effect: on CAMERA MODE: 1 input field, on PAL FILM MODE: 2 input fields; on NTSC FILM MODE 3 input fields Penalty for periodic structures Minimum vector length for null dbd penalty Null vector reliability threshold, makes detection of null vector in homogenous areas more reliable. Threshold value to adjust sensibility of null vector reliability: 1111: insensible : 0001: sensible to motion and noise 0000: off Additional penalty for null vector, if vector length exceeds length given by MENPTH and dbd of null vector is greater as a given threshold, which is defined by MENVRTH Penalty for update vectors Additional penalty for non-null vectors Vector smoothing on/off Unfiltered null dbd on/off Vector correction on/off
PERPEN MENPTH MENVRTH
52h 50h 59h
MENULLPEN
4Fh
MEPENUP MEADDPEN MESMOOTHON MENULLUNFON BVMCON
4Ch 4Ch 4Bh 4Bh 4Eh
Table 79
Output write IC Bus parameter
103
Micronas
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Preliminary Data Sheet
5.9
Motion compensation
In the SDA 9415 the motion estimation algorithm is combined with an advanced scan rate conversion algorithm. The Figure 45 shows the position of the fields as a function of the time for a 50 Hz sequence and a 100 Hz sequence. The information of the motion estimation (vector field) can be used for the generation of the additional fields. The A field is directly used as "a" field. The B field has the right position, but the wrong phase. The line-scanning pattern interpolation into a A field can be used as "c" field. The "b" and "d" field has to be generated using the vector field of the motion estimation.
100 Hz sequence an bn cn dn an+1 An+1 Bn 50 Hz sequence An
time
Figure 45
Timing of 100 Hz scan rate conversion
The Figure 46 shows a moving object as a function of the time. The position of the object in the b field is exactly half the position of the object in the A and B field. That`s why no double contours are visible.
An Bn 50 Hz sequence
an
bn
cn 100 Hz sequence
me02
time
Figure 46
Principles of motion compensation
The principle of the up conversion process is illustrated in the Figure 47 in case of the b field. Motion compensated pixels are fed to a 5-tap median filter. The background is that in case of correct motion vector, it can be expected that the two motion compensated pixels from both neighboring fields are identical. Consequently, either of the two is selected and a correctly motion compensated intermediate field results. In the figure below the vector ends on a non existing line. Therefore the pixels of the line before and after the non existing line are taken. Is the vector unreliable for the current pixel, the two
104 Micronas
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Preliminary Data Sheet
motion compensated pixels will be different, and the chance that the non-motion compensated field average at the output increases. The result is a graceful degradation of picture material in case of vector failure ("local fall back mode").
5-tap input, can be changed by FILSEL (non-motion compensated linear interpolation)
An
Bn
1/2 1/2
Median bn
Figure 47
Principles of motion compensation for the b field (FILSEL=0)
To generate an output sequence with a good motion portrayal the estimated vectors and the actual film mode information are used. Dependent on the film mode different output sequences are generated. The standard mode is camera mode. In this mode the input source provides a new motion phase on every field. The two other modes are called film mode PAL and NTSC, respectively. The arise from scanning cinematic source material for which only 24 frames per second are available. For film mode material scanned for 50 Hz standards always two successive fields have the same motion phase. The film source is reproduced with 25 Hz and each image is scanned twice to get an interlaced video signal. On NTSC film mode the 24 frames are scanned using the 2-3 pulldown method resulting in sequences, which contain alternating two and three successive fields with the same motion phase. In the next figures the three modes are illustrated for a onedimensional motion. The aim on motion compensation is to create an output field or frame sequence, which has a good motion portrayal. In the Figure 48, Figure 49 and Figure 50 the ideal motion portrayal is displayed as a dashed line. The output motion (solid line) should approach this ideal case. The deviation is marked as shadowed area. On camera mode no motion blurring occurs on source material (Figure 48: square curve). A simple non motion compensated scan rate conversion repeats previous motion phases and causes a motion blurring on 100/120 Hz output dependent on motion speed (Figure 48: triangle
105 Micronas
SDA 9415 - B13
Preliminary Data Sheet
curve). With motion compensation (Figure 48: rhomb curve) intermediate motion phases are calculated and the ideal curve is obtained, no motion blurring occurs.
1: camera mode
motion position (1D) Original 50/60Hz interlaced Simple non motion compensated SRC 100/120Hz interl. Motion compensated SRC 100/120Hz interl. Motion compensated SRC 50/60Hz progr.
50/60Hz step 100/120Hz step
time
Figure 48
Output sequence generation: Camera mode
A 50 Hz film mode input sequence already shows a motion blur (Figure 49: square curve). This artifact increases on higher velocities. Motion compensation techniques can reduce this effect under a visible threshold. Now the deviation from the ideal curve is minimized (Figure 49; rhomb curve). The result is an output motion potrayal, which is visibly smoother compared with the original input sequence. A 60 Hz input field sequence has motion artifacts on higher velocities (Figure 50: square curve) like the 50 Hz film mode but the blur is much more irregular caused by the 2-3 pulldown. The preferred application in this case is a 60 Hz progressive conversion. Here also the motion portrayal can be improved by creating a new motion phases (Figure 50: circle curve). Also this conversion results in an clearly improved motion potrayal. Evaluation shows a very large improvement of the Film motion portrayal.
106
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Preliminary Data Sheet
2: PAL film mode
motion position (1D) Original 50Hz interlaced motion compensated SRC 100Hz interl. motion compensated SRC 50Hz progr.
50Hz step 100Hz step
time
Figure 49
Output sequence generation: PAL film mode
3: NTSC film mode
motion position (1D) Original 60Hz interlaced
motion compensated SRC 120Hz interl.
motion compensated SRC 60Hz progressive
60Hz step 120Hz step
time
Figure 50
Output sequence generation: NTSC film mode
107
Micronas
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Preliminary Data Sheet
Original A field information Original B field information Motion compensated field Real motion course Ideal motion course
50/60Hz interlaced input 100/120Hz non motion compensated interlaced output 100/120Hz motion compensated interlaced output 50/60Hz motion compensated progressive output Deviation between real ideal motion course
The scan rate conversion of the colour difference signals is also vector based. As it was experimentally found that the dynamic resolution of the colour is not masked completely by the luminance, motion compensated chrominance processing is implemented. The chrominance motion compensation uses the vector results of the luminance motion estimation. The characteristic of the median filter can be changed by the IC Bus parameter FILSEL.
IC Bus parameter FILSEL
Sub address 4B
Description Filter select for VDU interpolation 11: Improved median based interfield interpolation: for use in SRC mode and for use with frame based upconversion or field based upconversion with two field memories (STOPMOM 0000, 0001, 0010, 1011, 1100, 1110, 1111 for RMODE 0 or 1) 10: median based interfield interpolation: [not recommended] 01: linear INTRAFIELD interpolation: interpolation (a0+a1)/2 or (b0+b1)/2 for use in SSC and MUP mode or for use with field based scan rate conversion and only one field memory (STOPMOM 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100 for RMODE 0 or 1) 00: linear INTERFIELD interpolation: (a0+a1+b0+b1)/4 [not recommended]
Table 80
Output write IC Bus parameter
5.10
Global motion, film mode and phase detection
For camera mode and film mode different scan rate conversion algorithms and motion estimation processes are valid. Therefore the information about camera mode or film mode and the corresponding phase are necessary to adapt the processing. In the SDA 9415 the film mode, film type and phase detection is based on the analysis of the motion
108 Micronas
SDA 9415 - B13
Preliminary Data Sheet
vectors from the estimator or the analysis of the field difference. It is expected that with film material broadcast in the 50 Hz television standard, motion will occur only every second field. Therefore the "vector activity" (VAC) in the SDA 9415 as sum of the absolute vector components which are larger as a threshold defined by the IC parameter MEMMINMOT (IC Bus sub address 4Bh) is accumulated . Depending on the sum, the actual detected mode (MOVMO, MOVTYP) and several IC Bus parameters (MEMINTH, MEMAXTH, SFMINTH, SFMAXTH) the actual field is decided to have motion or not. The table below explains the decision of the detection:
Actual field has motion
If [VAC > scmax * (MEMAXTH+1)] or [ (VAC > scmin * (MEMINTH+1)) and (VAC <= scmax * (MEMAXTH+1)) and MOVMO=0] [VAC <= scmin * (MEMINTH+1)] or [ (VAC > scmin * (MEMINTH+1)) and (VAC <= scmax * (MEMAXTH+1)) and MOVMO=1]
no motion
Table 81
Principles of global motion and film mode detection
The values scmin and scmax are scale factors which are defined by the table below:
SFMINTH/SFMAXTH 00 01 10 11
scmin/scmax 8 16 32 64
Table 82
Definition of scmin/scmax depending on SFMINTH/SFMAXTH
To avoid switching artifacts a temporal hysteresis is implemented. Temporal hysteresis means, that at least a certain number of fields defined by the IC Bus parameter MEMOHIST must fulfill the conditions for switching from camera mode to film mode or vice versa. The number of fields (NoFields) defined by the IC Bus parameter MEMOHIST can be calculated by the equation below:
NoFields =
2 MEMOHIST + 1
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Micronas
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Preliminary Data Sheet
Furthermore a global motion flag GMOTION is derived and the value MEMSTAT, which is proportional to the amount of blocks, which fulfill the condition mentioned above.
IC Bus parameter MOVPHIN 1: enabled 0: disabled MEMMINMOT MEMINTH MEMAXTH MEMOHIST SFMINTH SFMAXTH MEMMNDTH
Sub address 4Bh
Description Inversion of the Film phase signal
4Bh 4Dh 4Eh 4Fh 4Dh 4Dh 59h
Minimum vector threshold for film mode and global motion detection Threshold for detection of motion in camera mode Threshold for detection of motion in film mode History length of Film mode and global motion detection Scale factor for MEMINTH Scale factor for MEMAXTH Threshold for switching between the vector activity or the field difference as input for the film mode detection Use field difference as film mode detection input 1111: insensible to motion : 0001: sensible to motion 0000: use vector activity as film mode detection input
Table 83
Output write IC Bus parameter
110
Micronas
SDA 9415 - B13
Preliminary Data Sheet
IC Bus parameter MOVMO MOVPH
Sub address 7Eh 7Eh
Description 1: Film mode 0: camera mode Film mode phase: 1: Bn and An+1 has the same phase 0: An and Bn has the same phase Global motion detection 1: if no STILL scene is detected (minimum is: 1 field in motion of 32 fields in order) 0: if STILL scene is detected (32 fields in order without motion) Film mode type 1: NTSC film mode source with 24 motion phases per second (2-3 pull down) 0: PAL film mode source with 25 motion phases per second Statistic about motion blocks
GMOTION
7Eh
MOVTYP
7Eh
MEMSTAT
7Eh
Table 84
Output read IC Bus parameter
5.11
Vertical expansion
For every output field, the scan rate converter generates a progressive frame. Thus for every output field period, a progressively scanned frame compensated to the correct motion is used for vertical expansion in case of Micronas VDU. This yields a highly improved performance compared with an intra-field zoom. The table below defines the internal expansion factor ZOOM depending on the RMODE and VERINT IC Bus parameter.
VERINT IC Bus parameter IC Bus parameter
RMODE 0 1
ZOOM 2*(VERINT+1) (VERINT+1)
Table 85
Output write IC Bus parameter VERINT
The available expansion factors are listed in the table below.
111
Micronas
SDA 9415 - B13
Preliminary Data Sheet
100/120 Hz interlaced RMODE=0 VERINT 127 : 95 : 84 : 63 ZOOM 256 : 192 : 170 : 128
50/60 Hz progressive RMODE=1 ZOOM 128 : 96 : 85 : 64
real vertical expansion factor
1.00 : 1.33 : 1.50 : 2.00
Table 86
Examples of reachable expansion factors
The IC Bus parameter VPAN can be used to select the start line of the expansion. To expand the upper part of the incoming signal with the factor 2.0, VPAN should be set to zero. To expand the lower part, VPAN should be equal to 143. That means in case of VPAN=0 the first used line is line 1 and in case of VPAN=143 the first used line is line 144. Dependent on the IC Bus parameter VERINT a certain number of input lines of the input field is required. Therefore not all VPAN values are allowed. The formula below can be used to calculate the maximum allowed VPAN value depending on the chosen VERINT value.
VPANmax =
4 VERWIDTHM ae 1 - VERINT + 1 -o ------------------------------------128
Floor symbol means: take only integer part of x x Figure 51 Calculation of maximum VPAN value
112
Micronas
SDA 9415 - B13
Preliminary Data Sheet
IC Bus parameter VERINT VPAN
Sub address 47h 54h
Description Vertical expansion factor for master channel Vertical adjustment of the output picture for master channel
Table 87
Output write IC Bus parameter
5.12
Display processing
Signals IY_O IU_O IV_O
Pin number 87 84 90
Description Analog Y (luminance) output signal Analog U (chrominance) output signal Analog V (chrominance) output signal
Table 88
Output signals
The display processing part contains an integrated triple 9-bit DAC and performs digital enhancements and manipulations of the digital video component signal. The figure below shows the block diagram of the display processing part and the existing IC Bus parameters.
27 MHz BCOF HCOF CORING THRESY ASCENTLTI YBORDERD UBORDERD VBORDERD 54 MHz DACEN CHROM_AMP bddp
9
COARSDEL
YIN
8
Peaking
9
DLTI
9
9
Delay
9
9
Coarse Delay +7/-8 Delay
DAC
YO UO VO
OFC Framing
8:8:8
9 8
9
9
DAC
CIN
8
Delay
8
DCTI
8
4:4:4
9
9
Delay
9
DAC
THRESC ASCENTCTI
Figure 52
113
Block diagram of display processing
Micronas
SDA 9415 - B13
Preliminary Data Sheet
5.12.1
Peaking
The luminance peaking filter improves the over all frequency response of the luminance channel. It consists of two filters working in parallel. They have high pass (HP) and band pass (BP) characteristics. Their gain factors are separately programmable (IC Bus parameters BCOF 5Dh, HCOF 5Dh). The high pass and the band pass filters are equipped with a common coring algorithm. It is optimized to achieve a smooth display of grey scales, not to improve the signal-to-noise ratio. Therefore no artifacts are produced. Coring can be switched off (IC Bus parameter CORING, 5Ah). The figure below shows the block diagram of the peaking block.
BCOF HCOF CORING PEAKING BP gain_bp
peak_01
Coring HP Delay gain_hp
YIN
YPEAK
Figure 53
Block diagram peaking
The transfer functions of the separate filters are listed below:
High pass Transfer function: HHP(z) = 1/16 (1-z -1)4 Band pass Transfer function: HBP(z) = - 1/8 (1-z -2)
114
Micronas
SDA 9415 - B13
Preliminary Data Sheet
All pass Transfer function:HAP(z) = z -2 BCOF 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gain_bp 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.5 4 5 HCOF 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gain_hp 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.5 4 5
Table 89
Conversion table BCOF/HCOF to gain_bp/gain_hp
IC Bus parameter BCOF HCOF CORING
Sub address 5Dh 5Dh 5Ah
Description Gain of band pass filter Gain of high pass filter Coring for high- and band pass filter: 1: on 0: off
Table 90
Output write IC Bus parameters
5.12.2
Digital luminance transition improvement
A new digital algorithm is implemented to improve horizontal transitions of the luminance signals resulting in a better picture sharpness. A correction signal proportional to the slope of the detected horizontal transition of the input signal is added to the original input
115
Micronas
SDA 9415 - B13
Preliminary Data Sheet
signal. The amplitude of the correction signal is adjustable by the IC Bus parameter ASCENTLTI. The exact position of a luminance transition is calculated by detecting the corresponding zero transition of the second derivative of the luminance signal. Low pass filtering is performed to avoid noise sensitivity. The IC Bus parameter THRESY and THRESY_UP defines the sensitivity of the DLTI circuit. High values cause that only significant luminance transitions are improved. Small luminance variations remain unchanged.
THRESY 000 001 010 011 100 101 110 111
Sensitivity DLTI off 4 8 12 16 20 24 28
Table 91
IC Bus parameter THRESY
THRESHY_UP 00 01 10 11
Amplitude off 32 128 64
Table 92
IC Bus parameter THRESY_UP
116
Micronas
SDA 9415 - B13
Preliminary Data Sheet
ASCENTLTI 00 01 10 11
Amplitude 0.5 1 2 4
Table 93
IC Bus parameter ASCENTLTI
IC Bus parameter THRESY THRESY_UP ASCENTLTI
Sub address 5Eh 5Eh 5Ch
Description Defines lower sensitivity threshold of DLTI Defines upper sensitivity threshold of DLTI Defines amplitude of correction signal
Table 94
Output write IC Bus parameters
5.12.3
Digital colour transition improvement
A new digital algorithm is implemented to improve horizontal transitions of the chrominance signals resulting in a better picture sharpness. A correction signal proportional to the slope of the detected horizontal transition of the input signal is added to the original input signal. Different correction signals according to the bandwidth of the input signal are selected. The amplitude of the correction signal is adjustable by the IC Bus parameter ASCENTCTI. The exact position of a colour transition is calculated by detecting the corresponding zero transition of the second derivative of both chrominance signals. Low pass filtering is performed to avoid noise sensitivity. The IC Bus parameter THRESC modifies the sensitivity of the DCTI circuit. High values cause that only significant colour transitions are improved. Small colour variations remain unchanged. To eliminate "wrong colours" transitions, which are caused by over and undershoots at the chroma transition, the sharpened chroma signals are limited to a proper value automatically.
117
Micronas
SDA 9415 - B13
Preliminary Data Sheet
U or V chrominance signal t
cti
U or V
chrominance signal plus correction signal t chrominance signal plus correction signal with limitation t
Figure 54 Principles of DCTI
U or V
THRESC 00 01 10 11
Sensitivity DCTI off 4 8 12
Table 95
IC Bus parameter THRESC
118
Micronas
SDA 9415 - B13
Preliminary Data Sheet
ASCENTCTI 00 01 10 11
Amplitude 0.5 1 2 4
Table 96
IC Bus parameter ASCENTCTI
IC Bus parameter THRESC ASCENTCTI
Sub address 5Eh 5Ch
Description Defines sensitivity of DCTI Defines amplitude of correction signal
Table 97
Output write IC Bus parameters
119
Micronas
SDA 9415 - B13
Preliminary Data Sheet
5.12.4
Output format conversion
The SDA 9415 supports at the output side (digital output) the sample frequency relations of Y : (B-Y) : (R-Y): 4:2:2. The representation of the samples of the chrominance signal is programmable as positive dual code (unsigned, parameter TWOOUT=0) or two's complement code (TWOOUT=1, see "IC Bus" on page 123, IC bus parameter 5Ah).
Data Pin YOUT7 YOUT6 YOUT5 YOUT4 YOUT3 YOUT2 YOUT1 YOUT0 UVOUT7 UVOUT6 UVOUT5 UVOUT4 UVOUT3 UVOUT2 UVOUT1 UVOUT0 Table 98
4:2:2 Parallel Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 U07 U06 U05 U04 U03 U02 U01 U00 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 V07 V06 V05 V04 V03 V02 V01 V00
Output write parameters
X ab: X: signal component a: sample number b: bit number The digital output and the analog output can not be used together. Either the digital output or the analog output can be enabled. Therefore in the SDA 9415 a circuit is implemented, which allows only enabling of the digital or analog outputs.
120
Micronas
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Preliminary Data Sheet
Parameter DACEN 1: Enabled 0: Disabled DOUTEN 1: Enabled 0: Disabled Table 99
Subaddress 5Ah
Description Enables the Digital-to-Analog converter
5A
Enables the digital output pins
Output write parameters
5.12.5
Insertion facilities
Two different values are inserted into the video signal: black level and coloured background area. The black level insertion is done automatically in the SDA 9415. The black level is inserted in the horizontal and vertical blanking period. The second insertion facility produces a coloured background area on the display controlled by the IC Bus parameters YBORDERD, UBORDERD and VBORDERD.
IC Bus parameter YBORDERD
Sub address 5Ah
Description Y border value of display (Yborderd(3) Yborderd(2) Yborderd(1) Yborderd(0) 0 0 0 0 = 00010000 = 16), YBORDERD defines the 4 MSB's of a 8 bit value U border value of display (Uborderd(3) Uborderd(2) Uborderd(1) Uborderd(0) 0 0 0 0 = 10000000 = 128), UBORDERD defines the 4 MSB's of a 8 bit value V border value of display (Vborderd(3) Vborderd(2) Vborderd(1) Vborderd(0) 0 0 0 0 = 10000000 = 128), VBORDERD defines the 4 MSB's of a 8 bit value
UBORDERD
5Bh
VBORDERD
5Bh
Table 100
Output write IC Bus parameters
5.12.6
Coarse delay
Before Digital-to-Analog conversion an adjustment of the phase of the luminance signal can be performed (IC Bus parameter COARSDEL, 5Ch). The delay of the luminance can be varied by periods (-8, ...[1]... , +7) of the DAC clock (2*CLKD). This can be used to compensate different delay times of external analog filters.
121 Micronas
SDA 9415 - B13
Preliminary Data Sheet
IC Bus parameter COARSDEL
Sub address 5Ch
Description Delay of the luminance signal in relation to the chrominance signal in 2*CLKD clocks
Table 101
Output write IC Bus parameter
5.12.7
Digital-to-Analog conversion
Three 9-bit Digital-to-Analog converters are implemented. The DACs are short-circuit protected converters with current outputs. The full range output current of the IY_O, IU_O, IV_O channels (IOFR) is determined by the current IREF at the pin RREF_I by IOFR ~ 10 IREF . The voltage at the pin RREF_I is generated via pin UREF_I by an internal operational amplifier and follows the voltage at the pin UREF_I. Thus IREF is given by IREF ~ VUREF/RREF where RREF is a resistor between RREF_I and analog ground. Another way to define IREF is the application of a current sink at the RREF_I point. For recommended values of VUREF and IREF compare "Operating range" on page 177. For applications with lower requirements there is still another way to define IOFR: Connect pin UREF_I to the positive supply and apply a resistor against ground. Since in this operation mode the internal reference amplifier reaches saturation, the exact value of IREF is not exactly predictable.
IC Bus parameter CHROM_AMP
Sub address 5Eh
Description Chrominance amplification factor adjustment for DAC output 1: amplification factor 2 0: amplification factor 1
Table 102
Output write IC Bus parameter
122
Micronas
SDA 9415 - B13
Preliminary Data Sheet
5.13 5.13.1
IC Bus IC Bus slave address
Write Address: BCh 10111100 Read Address: BDh 10111101
5.13.2
IC Bus format
The SDA 9415 IC Bus interface acts as a slave receiver and a slave transmitter and provides two different access modes (write, read). All modes run with a sub address auto increment. The interface supports the normal 100 kHz transmission speed as well as the high speed 400 kHz transmission.
write:
S 1 0 1 1 1 1 0 0 A Sub address A Data Byte S: Start condition A: Acknowledge P: Stop condition NA: Not Acknowledge A ***** A P
read:
S 1 0 1 1 1 1 0 0 A Sub address A S 1 0 1 1 1 1 0 1 A Data Byte A Data Byte NA P
The transmitted data are internally stored in registers. The master has to write a don't care byte to the sub address FFh (store command) to make the register values available for the SDA 9415. To have a defined time step, where the data will be available, the data are made valid with the incoming V-sync VINM or VINS or with the next OPSTARTM pulse, which is an internal signal and indicates the start of a new output cycle. The sub addresses, where the data are made valid with the VINM signal are indicated in the overview of the sub addresses with VIM", where the data are made valid with the VINS are indicated with "VIS" and where the data are made valid with the OPSTARTM are indicated with OS". The IC parameter VIMSTATUS, VISSTATUS and OSSTATUS (sub address 80h, 81h, 82h) reflect the state of the register values. If these bits are read as
123
Micronas
SDA 9415 - B13
Preliminary Data Sheet
'1', then the store command was sent, but the data aren't made available yet. If these bits are '0' then the data were made valid and a new write or read cycle can start. The bits VIMSTATUS, VISSTATUS and OSSTATUS may be checked before writing or reading new data, otherwise data can be lost by overwriting. Furthermore the bits NMSTATUS (status of noise measurement: NOISEME) and LBDSTATUS (status of letter box IC Bus parameters: SLAA, ELAA, STATUS_SLAA, STATUS_ELAA, RELY) exist. NMSTATUS signalizes a new value for NOISEME. So if NMSTATUS is read as '0' the current noise measurement has not been updated. If the NMSTATUS is read as '1' a new noise measurement value can be read. LBSTATUS signalizes at least a change of one of the IC Bus parameters: SLAA, ELAA, STATUS_SLAA, STATUS_ELAA, RELY. If the LBDSTATUS is read as '0' none of the IC Bus parameters has changed its value. If the LBDSTATUS is read as '1' at least one of the IC Bus parameters has changed its value. The transmitted data are internally stored in registers. Writing or reading from a not existing register is permitted and does not generate a fault by the IC. After switching on the IC (after reset), all bits of the SDA 9415 are set to defined states. Particularly :
Sub address Default value 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 00h 00h 00h 00h 61h 88h 00h 40h 00h 00h 00h 69h 00h 90h B4h B4h 90h 00h 50h R/W W W W W W W W W W W W W W W W W W W W Take over VIM VIM VIM VIM VIM VIM VIM VIM VIM VIM VIM VIM VIM VIM VIM VIM VIM VIM VIM Sub address Default value 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 48h 9Ch 00h 00h 00h 00h 00h 5Ah B4h 48h 90h 00h 5Ah B4h B0h 10h 7Fh 00h 00h R/W W W W W W W W W W W W W W W W W W W W Take over OS OS OS OS OS OS OS OS OS OS OS OS OS OS OS OS OS OS OS
124
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address Default value 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 not used 09h FFh 00h FFh 81h 01h 1Ch AAh 78h C6h 32h 57h 1Ch not used 00h 00h 00h 00h 61h 88h 00h 40h 00h 00h 00h E9h 00h 90h B4h B4h 90h 00h 28h
R/W
Take over
Sub address Default value 4A 00h 8Dh 88h 87h 3Fh 38h 56h 64h 3Ah 08h 00h 08h 78h 02h 02h 00h 21h 88h 58h 44h 73h 20h not used
R/W W W W W W W W W W W W W W W W W W W W W W W
Take over OS OS OS OS OS OS OS OS OS OS OS OS OS OS OS OS OS OS OS OS OS OS
W W W W W W W W W W W W W
VIM VIM VIM VIM VIM VIM VIM VIM VIM VIM VIM VIM VIM
4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58
W W W W W W W W W W W W W W W W W W W
VIS VIS VIS VIS VIS VIS VIS VIS VIS VIS VIS VIS VIS VIS VIS VIS VIS VIS VIS
59 5A 5B 5C 5D 5E 5F 60-77 78 79 7A 7B 7C 7D 7E 7F 80 81 82
R R R R R R R R R R R
125
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address Default value 35 36 00h 16h
R/W W W
Take over OS OS
Sub address Default value 83-FE FF not used
R/W
Take over
W
R/W: R - Read register; W - Write Register; R/W - Read and Write Register; Take over: VIM - take over with VINM; VIS - take over with VINS; OS - take over with OPSTARTM
5.13.3
IC Bus commands
Subadd. Data Byte (Hex.) D7 D6 D5 D4 D3 D2 D1 D0
00
x
x
x
PLLMOFF PLLM IPOSYM4 VHCOM IPOSXM4 VHCOM RIBORDM2 VHCOM FORCOLM VHCOM
PLLMRA3 PLLM IPOSYM3 VHCOM IPOSXM3 VHCOM RIBORDM1 VHCOM
PLLMRA2 PLLM IPOSYM2 VHCOM IPOSXM2 VHCOM RIBORDM0 VHCOM
PLLMRA1 PLLM IPOSYM1 VHCOM IPOSXM1 VHCOM CHFILM1 VHCOM
PLLMRA0 PLLM IPOSYM0 VHCOM IPOSXM0 VHCOM CHFILM0 VHCOM
01
IPOSYM7 VHCOM IPOSXM7 VHCOM LEBORDM2 VHCOM DELM2 IFC
IPOSYM6 VHCOM IPOSXM6 VHCOM LEBORDM1 VHCOM DELM1 IFC
IPOSYM5 VHCOM IPOSXM5 VHCOM LEBORDM0 VHCOM DELM0 IFC
02
03
04
YBORDERM3 YBORDERM2 YBORDERM1 YBORDERM0 VHCOM VHCOM VHCOM VHCOM VBORDERM3 VBORDERM2 VBORDERM1 VBORDERM0 VHCOM VHCOM VHCOM VHCOM LWBORDM3 VHCOM INTHM8 VHCOM INTHM0 VHCOM INTVM4 VHCOM LWBORDM2 VHCOM INTHM7 VHCOM DEZHM2 VHCOM INTVM3 VHCOM LWBORDM1 VHCOM INTHM6 VHCOM DEZHM1 VHCOM INTVM2 VHCOM LWBORDM0 VHCOM INTHM5 VHCOM DEZHM0 VHCOM INTVM1 VHCOM
05
UBORDERM3 UBORDERM2 UBORDERM1 UBORDEM0 VHCOM VHCOM VHCOM VHCOM UPBORDM3 VHCOM INTHM12 VHCOM INTHM4 VHCOM INTVM8 VHCOM UPBORDM2 VHCOM INTHM11 VHCOM INTHM3 VHCOM INTVM7 VHCOM UPBORDM1 VHCOM INTHM10 VHCOM INTHM2 VHCOM INTVM6 VHCOM UPBORDM0 VHCOM INTHM9 VHCOM INTHM1 VHCOM INTVM5 VHCOM
06
07
08
09
126
Micronas
SDA 9415 - B13
Preliminary Data Sheet
0A
INTVM0 VHCOM x
DEZVM2 VHCOM FORMATM1 IFC NAPIPDLM6 ISC ALPFM6 ISC APPLM6 ISC APPLIPM6 ISC ALPFIPM6 ISC VINDELM4 ISC NALIPM4 ISC x
DEZVM1 VHCOM FORMATM0 IFC NAPIPDLM5 ISC ALPFM5 ISC APPLM5 ISC APPLIPM5 ISC ALPFIPM5 ISC VINDELM3 ISC NALIPM3 ISC x
DEZVM0 VHCOM FIEINVM ISC NAPIPDLM4 ISC ALPFM4 ISC APPLM4 ISC APPLIPM4 ISC ALPFIPM4 ISC VINDELM2 ISC NALIPM2 ISC x
YPEAKM1 VHCOM
YPEAKM0 VHCOM
CPEAKM1 VHCOM NAPIPPHM0 ISC NAPIPDLM1 ISC ALPFM1 ISC APPLM1 ISC APPLIPM1 ISC ALPFIPM1 ISC VINPOLM ISC CHRFORM1 VHCOM x
CPEAKM0 VHCOM TWOINM IFC NAPIPDLM0 ISC ALPFM0 ISC APPLM0 ISC APPLIPM0 ISC ALPFIPM0 ISC HINPOLM ISC CHRFORM0 VHCOM x
0B
VCRMODEM NAPIPPHM1 ISC ISC NAPIPDLM3 ISC ALPFM3 ISC APPLM3 ISC APPLIPM3 ISC ALPFIPM3 ISC VINDELM1 ISC NALIPM1 ISC x NAPIPDLM2 ISC ALPFM2 ISC APPLM2 ISC APPLIPM2 ISC ALPFIPM2 ISC VINDELM0 ISC NALIPM0 ISC x
0C
NAPIPDLM7 ISC ALPFM7 ISC APPLM7 ISC APPLIPM7 ISC ALPFIPM7 ISC VINDELM5 ISC x
0D
0E
0F
10
11
12
13
x
14
x
x
NMLINE4 TSNR TNRCLY1 TSNR TNRKOY1 TSNR TNRVAY1 TSNR TNRHOY4 TSNR TNRHOC4 TSNR PANAST3 TSNR OPDELM5 ISC
NMLINE3 TSNR TNRCLY0 TSNR TNRKOY0 TSNR TNRVAY0 TSNR TNRHOY3 TSNR TNRHOC3 TSNR PANAST2 TSNR OPDELM4 ISC
NMLINE2 TSNR TNRCLC3 TSNR TNRKOC3 TSNR TNRVAC3 TSNR TNRHOY2 TSNR TNRHOC2 TSNR PANAST1 TSNR OPDELM3 ISC
NMLINE1 TSNR TNRCLC2 TSNR TNRKOC2 TSNR TNRVAC2 TSNR TNRHOY1 TSNR TNRHOC1 TSNR PANAST0 TSNR OPDELM2 ISC
NMLINE0 TSNR TNRCLC1 TSNR TNRKOC1 TSNR TNRVAC1 TSNR TNRHOY0 TSNR TNRHOC0 TSNR NRON TSNR OPDELM1 ISC
NMALG TSNR TNRCLC0 TSNR TNRKOC0 TSNR TNRVAC0 TSNR TNRFIY TSNR TNRFIC TSNR DTNRON TSNR OPDELM0 ISC
15
TNRCLY3 TSNR TNRKOY3 TSNR TNRVAY3 TSNR TNRSEL TSNR x
TNRCLY2 TSNR TNRKOY2 TSNR TNRVAY2 TSNR TNRHOY5 TSNR TNRHOC5 TSNR PANAON VHCOM OPDELM6 ISC
16
17
18
19
1A
SNRON TSNR OPDELM7 ISC
1B
127
Micronas
SDA 9415 - B13
Preliminary Data Sheet
1C
TH_DN_BN5 LBD TH_LB3 LBD x
TH_DN_BN4 LBD TH_LB2 LBD TH_AA6 LBD
TH_DN_BN3 LBD TH_LB1 LBD TH_AA5 LBD
TH_DN_BN2 LBD TH_LB0 LBD TH_AA4 LBD
TH_DN_BN1 LBD TH_ALB3 LBD TH_AA3 LBD
TH_DN_BN0 LBD TH_ALB2 LBD TH_AA2 LBD TH_AUNS2 LBD TH_MA_AA1 LBD x
TH_LB5 LBD TH_ALB1 LBD TH_AA1 LBD TH_AUNS1 LBD TH_MA_AA0 LBD x
TH_LB4 LBD TH_ALB0 LBD TH_AA0 LBD TH_AUNS0 LBD VOLBD LBD x
1D
1E
1F
TH_MUNSL3 TH_MUNSL2 TH_MUNSL1 TH_MUNSL0 TH_AUNS3 LBD LBD LBD LBD LBD x x x TH_MA_AA3 LBD x TH_MA_AA2 LBD x
20
21
x
x
x
22
x
x
x
PLLSOFF PLLS IPOSYS4 VHCOM IPOSXS4 VHCOM RIBORDS2 VHCOM FORCOLS VHCOM
PLLSRA3 PLLS IPOSYS3 VHCOM IPOSXS3 VHCOM RIBORDS1 VHCOM
PLLSRA2 PLLS IPOSYS2 VHCOM IPOSXS2 VHCOM RIBORDS0 VHCOM
PLLSRA1 PLLS IPOSYS1 VHCOM IPOSXS1 VHCOM CHFILS1 VHCOM
PLLSRA0 PLLS IPOSYS0 VHCOM IPOSXS0 VHCOM CHFILS0 VHCOM
23
IPOSYS7 VHCOM IPOSXS7 VHCOM LEBORDS2 VHCOM DELS2 IFC
IPOSYS6 VHCOM IPOSXS6 VHCOM LEBORDS1 VHCOM DELS1 IFC
IPOSYS5 VHCOM IPOSXS5 VHCOM LEBORDS0 VHCOM DELS0 IFC
24
25
26
YBORDERS3 YBORDERS2 YBORDERS1 YBORDERS0 VHCOM VHCOM VHCOM VHCOM
27
UBORDERS3 UBORDERS2 UBORDERS1 UBORDERS0 VBORDERS3 VBORDERS2 VBORDERS1 VBORDERS0 VHCOM VHCOM VHCOM VHCOM VHCOM VHCOM VHCOM VHCOM UPBORDS3 VHCOM INTHS12 VHCOM INTHS4 VHCOM INTVS8 VHCOM INTVS0 VHCOM SLAVECON IFC UPBORDS2 VHCOM INTHS11 VHCOM INTHS3 VHCOM INTVS7 VHCOM DEZVS2 VHCOM FORMATS1 IFC UPBORDS1 VHCOM INTHS10 VHCOM INTHS2 VHCOM INTVS6 VHCOM DEZVS1 VHCOM FORMATS0 IFC UPBORDS0 VHCOM INTHS9 VHCOM INTHS1 VHCOM INTVS5 VHCOM DEZVS0 VHCOM FIEINVS ISC LWBORDS3 VHCOM INTHS8 VHCOM INTHS0 VHCOM INTVS4 VHCOM YPEAKS1 VHCOM VCRMODES ISC LWBORDS2 VHCOM INTHS7 VHCOM DEZHS2 VHCOM INTVS3 VHCOM YPEAKS0 VHCOM NAPIPPHS1 ISC LWBORDS1 VHCOM INTHS6 VHCOM DEZHS1 VHCOM INTVS2 VHCOM CPEAKS1 VHCOM NAPIPPHS0 ISC LWBORDS0 VHCOM INTHS5 VHCOM DEZHS0 VHCOM INTVS1 VHCOM CPEAKS0 VHCOM TWOINS IFC
28
29
2A
2B
2C
2D
128
Micronas
SDA 9415 - B13
Preliminary Data Sheet
2E
NAPIPDLS7 ISC ALPFS7 ISC APPLS7 ISC APPLIPS7 ISC ALPFIPS7 ISC VINDELS5 ISC NALIPS6 ISC HOUTDEL7 OSC NALOPD7 OSC x
NAPIPDLS6 ISC ALPFS6 ISC APPLS6 ISC APPLIPS6 ISC ALPFIPS6 ISC VINDELS4 ISC NALIPS5 ISC HOUTDEL6 OSC NALOPD6 OSC ALPFOPD6 OSC LPFOP6 OSC NAPOPD6 OSC HORPOSM6 OSC HORPOSS6 OSC VERPOSM6 OSC VERPOSS6 OSC
NAPIPDLS5 ISC ALPFS5 ISC APPLS5 ISC APPLIPS5 ISC ALPFIPS5 ISC VINDELS3 ISC NALIPS4 ISC HOUTDEL5 OSC NALOPD5 OSC ALPFOPD5 OSC LPFOP5 OSC NAPOPD5 OSC HORPOSM5 OSC HORPOSS5 OSC VERPOSM5 OSC VERPOSS5 OSC
NAPIPDLS4 ISC ALPFS4 ISC APPLS4 ISC APPLIPS4 ISC ALPFIPS4 ISC VINDELS2 ISC NALIPS3 ISC HOUTDEL4 OSC NALOPD4 OSC ALPFOPD4 OSC LPFOP4 OSC NAPOPD4 OSC HORPOSM4 OSC HORPOSS4 OSC VERPOSM4 OSC VERPOSS4 OSC
NAPIPDLS3 ISC ALPFS3 ISC APPLS3 ISC APPLIPS3 ISC ALPFIPS3 ISC VINDELS1 ISC NALIPS2 ISC HOUTDEL3 OSC NALOPD3 OSC ALPFOPD3 OSC LPFOP3 OSC NAPOPD3 OSC HORPOSM3 OSC HORPOSS3 OSC VERPOSM3 OSC VERPOSS3 OSC
NAPIPDLS2 ISC ALPFS2 ISC APPLS2 ISC APPLIPS2 ISC ALPFIPS2 ISC VINDELS0 ISC NALIPS1 ISC HOUTDEL2 OSC NALOPD2 OSC ALPFOPD2 OSC LPFOP2 OSC NAPOPD2 OSC HORPOSM2 OSC HORPOSS2 OSC VERPOSM2 OSC VERPOSS2 OSC
NAPIPDLS1 ISC ALPFS1 ISC APPLS1 ISC APPLIPS1 ISC ALPFIPS1 ISC VINPOLS ISC NALIPS0 ISC HOUTDEL1 OSC NALOPD1 OSC ALPFOPD1 OSC LPFOP1 OSC NAPOPD1 OSC HORPOSM1 OSC HORPOSS1 OSC VERPOSM1 OSC VERPOSS1 OSC
NAPIPDLS0 ISC ALPFS0 ISC APPLS0 ISC APPLIPS0 ISC ALPFIPS0 ISC HINPOLS ISC CHRFORS VHCOM HOUTDEL0 OSC NALOPD0 OSC ALPFOPD0 OSC LPFOP0 OSC NAPOPD0 OSC HORPOSM0 OSC HORPOSS0 OSC VERPOSM0 OSC VERPOSS0 OSC
2F
30
31
32
33
34
35
36
37
38
LPFOP7 OSC NAPOPD7 OSC HORPOSM7 OSC HORPOSS7 OSC VERPOSM7 OSC VERPOSS7 OSC x
39
3A
3B
3C
3D
3E
HORWIDTHM6 HORWIDTHM5 HORWIDTHM4 HORWIDTHM3 HORWIDTHM2 HORWIDTHM1 HORWIDTHM0 OSC OSC OSC OSC OSC OSC OSC
3F
HORWIDTHS7 HORWIDTHS6 HORWIDTHS5 HORWIDTHS4 HORWIDTHS3 HORWIDTHS2 HORWIDTHS1 HORWIDTHS0 OSC OSC OSC OSC OSC OSC OSC OSC
129
Micronas
SDA 9415 - B13
Preliminary Data Sheet
40
x
VERWIDTHM6 VERWIDTHM5 VERWIDTHM4 VERWIDTHM3 VERWIDTHM2 VERWIDTHM1 VERWIDTHM0 OSC OSC OSC OSC OSC OSC OSC
41
VERWIDTHS7 VERWIDTHS6 VERWIDTHS5 VERWIDTHS4 VERWIDTHS3 VERWIDTHS2 VERWIDTHS1 VERWIDTHS0 OSC OSC OSC OSC OSC OSC OSC OSC BLANDEL7 OSC x BLANDEL6 OSC APPLOPD6 OSC BLANLEN6 OSC PPLOP6 OSC x BLANDEL5 OSC APPLOPD5 OSC BLANLEN5 OSC PPLOP5 OSC x BLANDEL4 OSC APPLOPD4 OSC BLANLEN4 OSC PPLOP4 OSC PPLOP8 OSC VERINT4 OSC STOPMOM3 OSC INTMODE0 OSC VOUTPOL OSC MOVPHINV ME MEPENUP0 ME SFMINTH0 ME MEMAXTH4 ME BLANDEL3 OSC APPLOPD3 OSC BLANLEN3 OSC PPLOP3 OSC CAPPM1 OSC VERINT3 OSC STOPMOM2 OSC BLANKPOL OSC HOUTPOL OSC BLANDEL2 OSC APPLOPD2 OSC BLANLEN2 OSC PPLOP2 OSC CAPPM0 OSC VERINT2 OSC STOPMOM1 OSC ADOPMOM2 OSC STOPMOS2 OSC BLANDEL1 OSC APPLOPD1 OSC BLANLEN1 OSC PPLOP1 OSC CAPPS1 OSC VERINT1 OSC STOPMOM0 OSC ADOPMOM1 OSC STOPMOS1 OSC BLANDEL0 OSC APPLOPD0 OSC BLANLEN0 OSC PPLOP0 OSC CAPPS0 OSC VERINT0 OSC RMODE OSC ADOPMOM0 OSC STOPMOS0 OSC
42
43
44
BLANLEN7 OSC PPLOP7 OSC x
45
46
47
x
VERINT6 OSC x
VERINT5 OSC x
48
x
49
INTMODE3 OSC x
INTMODE2 OSC VOUTFR OSC FILSEL1 SRCM MEPENUP2 ME SFMAXTH0 ME x
INTMODE1 OSC HOUTFR OSC FILSEL0 SRCM MEPENUP1 ME SFMINTH1 ME BVMCON ME
4A
4B
PRIORMS MUX MEPENUP3 ME SFMAXTH1 ME x
MESMOOTH- MENULLUNON ME FON ME
MEMINMOT1 MEMINMOT0 ME ME
4C
MEADDPEN3 MEADDPEN2 MEADDPEN1 MEADDPEN0 ME ME ME ME MEMINTH3 ME MEMINTH2 ME MEMINTH1 ME MEMINTH0 ME
4D
4E
MEMMAXTH3 MEMMAXTH2 MEMMAXTH1 MEMMAXTH0 ME ME ME ME
4F
MEMOHIST3 MEMOHIST2 MEMOHIST1 MEMOHIST0 MENULLPEN3 MENULLPEN2 MENULLPEN1 MENULLPEN0 ME ME ME ME ME ME ME ME MEANBP1 ME MEANRG1 ME MEANBP0 ME MEANRG0 ME MEANMP1 ME MEANMP0 ME MENPTH2 ME MENPTH1 ME MENPTH0 ME MEPERINF ME
50
51
MEHPERTH2 MEHPERTH1 MEHPERTH0 MEVPERTH2 MEVPERTH1 MEVPERTH0 ME ME ME ME ME ME
130
Micronas
SDA 9415 - B13
Preliminary Data Sheet
52
x
BVMRES ME REFRPER0 MC VPAN6 MC RSHFTM MC
PERPEN2 ME MEMOP1 MC VPAN5 MC RSHFTS MC
PERPEN1 ME MEMOP0 MC VPAN4 MC SHFTSTEP3 MC
PERPEN0 ME MASTERON MC VPAN3 MC SHFTSTEP2 MC
VECDISON SRCM SLAVEON MC VPAN2 MC SHFTSTEP1 MC
THYON ME MEMRDM MC VPAN1 MC SHFTSTEP0 MC
RESMOV ME MEMRDS MC VPAN0 MC MASTSLA MC
53
REFRPER1 MC VPAN7 MC REFRON MC
54
55
56
PROG_THRES6 PROG_THRES5 PROG_THRES4 PROG_THRES3 PROG_THRES2 PROG_THRES1 PROG_THRES0 MASLSHFT MC MC MC MC MC MC MC MC
57
x
x
x
MEMWRS MC MEMWRM MC
FREEZES MC FREEZEM MC
WRFLDS MC WRFLDM MC MENVRTH2 ME
ORGMEMS MC ORGMEMM MC MENVRTH1 ME
VERRESS MC VERRESM MC MENVRTH0 ME
58
x
x
x
59
MEMMNDTH3 MEMMNDTH2 MEMMNDTH1 MEMMNDTH0 MENVRTH3 ME ME ME ME ME DOUTEN DAC TWOOUT OFC DACEN DAC CORING PK
5A
YBORDERD3 YBORDERD2 YBORDERD1 YBORDERD0 OFC OFC OFC OFC
5B
UBORDERD3 UBORDERD2 UBORDERD1 UBORDERD0 VBORDERD3 VBORDERD2 VBORDERD1 VBORDERD0 OFC OFC OFC OFC OFC OFC OFC OFC ASCENTLTI1 ASCENTLTI0 ASCENTCTI1 ASCENTCTI0 COARSDEL3 COARSDEL2 COARSDEL1 COARSDEL0 LTI LTI CTI CTI CD CD CD CD BCOF3 PK BCOF2 PK BCOF1 PK BCOF0 PK HCOF3 PK THRESC0 CTI PLLDRA3 PLLD x HCOF2 PK THRESY2 LTI PLLDRA2 PLLD x HCOF1 PK THRESY1 LTI PLLDRA1 PLLD x HCOF0 PK THRESY0 LTI PLLDRA0 PLLD x
5C
5D
5E
CHROM_AMP THRESY_UP1 THRESY_UP0 THRESC1 DAC LTI LTI CTI x CLKMDEN PLLD x CLKOUTON PLLD x PLLDOFF PLLD x
5F
60-77
x
78
SLAA7 LBD ELAA7 LBD NOISEME4 TSNR
SLAA6 LBD ELAA6 LBD NOISEME3 TSNR
SLAA5 LBD ELAA5 LBD NOISEME2 TSNR
SLAA4 LBD ELAA4 LBD NOISEME1 TSNR
SLAA3 LBD ELAA3 LBD NOISEME0 TSNR
SLAA2 LBD ELAA2 LBD VERSION2 IC
SLAA1 LBD ELAA1 LBD VERSION1 IC
SLAA0 LBD ELAA0 LBD VERSION0 IC
79
7A
131
Micronas
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Preliminary Data Sheet
7B
x
x
x
x
STATUS_SLA STATUS_ELA A LBD A LBD x x
RELY LBD NMSTATUS TSNR x MEMSTAT1 ME x
TVMODEM ISC LBDSTATUS LBD TVMODES ISC MEMSTAT0 ME SHIFTACT MC VIMSTATUS IC VISSTATUS IC OSSTATUS IC
7C
x
x
x
x
7D
x MOVMO ME x
x MOVPH ME x
x GMOTION ME x
x MOVTYP ME x
x MEMSTAT3 ME x
x MEMSTAT2 ME x
7E
7F
80
x
x
x
x
x
x
x
81
x
x
x
x
x
x
x
82
x
x
x
x
x
x
x
x = don't care ISC - Input sync controller block IFC - Input format conversion block OSC - Output sync controller block OFC - Output format conversion block LBD - Letter box detection block VHCOM - Vertical-horizontal compression/expansion block TSNR - Temporal noise reduction block ME - Motion estimation block PK - Peaking LTI - Luminance transition improvement block CTI - Chrominance transition improvement block CD - Coarse Delay block MC - Memory controller PLLM - Clock doubling block master PLLS - Clock doubling block slave PLLD - Clock doubling block display IC Bus block
132
Micronas
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Preliminary Data Sheet
5.13.4
Detailed description
Default values are underlined.
Sub address 00 Bit D7...D5 D4 Name x Function xxx
PLLMOFF Only for test purposes, do not use in normal mode PLLM (Clock doubling): 1: off 0: on PLLMRA Only for test purposes, do not use in normal mode PLLM range, only for test purposes [PPLMRA=0]
D3...D0
Sub address 01 Bit D7...D0 Name IPOSYM Function Vertical Picture Position in the Memory for Master Picture resolution: 1 line [IPOSYM=0] - upper position
Sub address 02 Bit D7...D0 Name IPOSXM Function Horizontal Picture Position in the Memory for Master Picture resolution: 4 pixel [IPOSXM=0] - left position
Sub address 03 Bit D7...D5 Name
LEBORDM
Function Amount of left border pixels by horizontal compression master: 4*LEBORDM [LEBORDM=0]
133
Micronas
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Preliminary Data Sheet
Sub address 03 Bit D4...D2 D1...D0 Name Function RIBORDM Amount of right border pixels by horizontal compression master: 4*RIBORDM [RIBORDM=0] CHFILM Chrominance Filter Master channel on/off 11: vertical and horizontal filter on (only valid for DEZHM=DEZVM=0) 10: horizontal filter on (only valid for DEZHM=0) 01: vertical filter on (only valid for DEZVM=0) 00: off
Sub address 04 Bit D7...D5 Name DELM Function Adjustable delay between luminance and chrominance data master channel: 111:+4 110:+3 101:+2 100:+1 011: 0 010: -1 001: -2 000: -3 Force colour master channel 1: on 0: off Y border value (Yborder(3) Yborder(2) Yborder(1) Yborder(0) 0 0 0 0 = 00010000 = 16), YBORDERM defines the 4 MSB's of a 8 bit value
D4
FORCOLM
D3...D0
YBORDERM
134
Micronas
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Preliminary Data Sheet
Sub address 05 Bit D7...D4 Name
UBORDERM
Function U border value (Uborder(3) Uborder(2) Uborder(1) Uborder(0) 0 0 0 0 = 10000000 = 128), UBORDERM defines the 4 MSB's of a 8 bit value V border value (Vborder(3) Vborder(2) Vborder(1) Vborder(0) 0 0 0 0 = 10000000 = 128), VBORDERM defines the 4 MSB's of a 8 bit value
D3...D0
VBORDERM
Sub address 06 Bit D7...D4 D3...D0 Name
UPBORDM
Function Amount of upper border lines by vertical compression master: [UPBORDM=0] Amount of lower border lines by vertical compression master: [LWBORDM=0]
LWBORDM
Sub address 07 Bit D7...D0 Name INTHM Function Interpolation factor for horizontal compression/expansion master: [INTHM(12...5)=64]
Sub address 08 Bit D7...D3 Name INTHM Function Interpolation factor for horizontal compression/expansion master: INTHM(4...0)=0
135
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 08 Bit D2...D0 Name DEZHM Function Decimation factor for horizontal compression/expansion master: 111: Factor 16 110: Factor 8 101: Factor 4 100: Factor 2 011: not defined 010: not defined 001: Factor 1 000: Bypass
Sub address 09 Bit D7...D0 Name INTVM Function Interpolation factor for vertical compression master: INTVM+512 [INTVM(8...1)=0]
Sub address 0A Bit D7 Name INTVM Function Interpolation factor for vertical compression master: INTVM+512 [INTVM(0)=0] Decimation factor for vertical compression master: 111: Factor 16 110: Factor 8 101: Factor 4 100: Factor 2 011: not defined 010: not defined 001: Factor 1 000: Bypass
D6...D4
DEZVM
136
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 0A Bit D3...D2 Name YPEAKM Function Vertical peaking factor for luminance signal master: 11: Factor 4 10: Factor 2 01: Factor 1 00: off Vertical peaking factor for chrominance signal master: 11: Factor 4 10: Factor 2 01: Factor 1 00: off
D1...D0
CPEAKM
Sub address 0B Bit D7 D6...D5 Name x
FORMATM
Function x Input format master: 11: full CCIR 656 10: CCIR 656 only data, H- and V-sync according CCIR656 01: CCIR 656 only data, H- and V-sync according PAL/NTSC 00: 4:2:2 Field polarity inversion master: 1: Field A=1, Field B=0 0: Field A=0, Field B=1 Input filtering of the incoming field signal master: 1: on 0: off
D4
FIEINVM
D3
VCRMODEM
D2...D1
Number of not active pixels from external HINM to the input data (LSBs of in system clocks of CLKM: NAPLIPM) Distance(HINM to input data) = (NAPIPDLM*4+NAPIPPHM+8) [NAPIPPHM = 0]
NAPIPPHM
D0
TWOINM
Chrominance input format master: 1: 2's complement input (-128...127) 0: unsigned input (0...255) inside the SDA 9415 the data are always processed as unsigned data
137
Micronas
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Preliminary Data Sheet
Sub address 0C Bit D7...D0 Name
NAPIPDLM
Function
Number of not active pixels from HINM to the input data in (MSBs of system clocks of CLKM: NAPLIPM) Distance(HINM to input data) = (4 * NAPIPDLM + NAPIPPHM + 8) [NAPIPDLM= 0]
Sub address 0D Bit D7...D0 Name ALPFM Function Number of active lines per field after vertical compression master: Active lines = ALPFM * 2 [ALPFM=144]
Sub address 0E Bit D7...D0 Name APPLM Function Number of active pixels per line in the input data stream after horizontal expansion/compression in system clocks of CLKM: Active pixels = APPLM*8 [APPLM = 180]
Sub address 0F Bit D7...D0 Name APPLIPM Function Number of active pixels per line in the input data stream in system clocks of CLKM: Active pixels = APPLIPM*8 [APPLIPM = 180]
138
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 10 Bit D7...D0 Name ALPFIPM Function Number of active lines per field in the input data stream master: Active lines = ALPFIPM * 2 [ALPFIPM=144]
Sub address 11 Bit D7...D2 Name VINDELM Function VINM input delay: Delay(VINM to internal V-sync) = (128 * VINDELM + 1)*Tclkm [VINDELM = 0] VINM polarity: 1: low active 0: high active
D1
VINPOLM
D0
HINPOLM HINM polarity: 1: low active 0: high active
Sub address 12 Bit D7 D6...D2 Name x NALIPM Function x Number of not active lines per field in the input data stream master: Not active lines = NALIPM+3 [NALIPM= 20] Chrominance Format Master Channel: 11: not defined 10: reserved 01: 4:2:0 00: 4:1:1
D1...D0
CHRFOR M
139
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 14 Bit D7...D6 D5...D1 D0 Name x NMLINE NMALG Function xx Line for noise measurement (only valid for NMALG=1) [NMLINE = 4] Noise measurement algorithm: 1: measurement during vertical blanking period (line can be defined by NMLINE) 0: measurement in the active picture
Sub address 15 Bit D7...D4 Name TNRCLY Function Temporal noise reduction of luminance: classification 1111: slight noise reduction : 0000: strong noise reduction Temporal noise reduction of chrominance: classification 1111: slight noise reduction : 0000: strong noise reduction
D3...D0
TNRCLC
Sub address 16 Bit D7...D4 D3...D0 Name TNRKOY TNRKOC Function Temporal noise reduction of luminance: Vertical shift of the motion detector characteristic [TNRKOY=0] Temporal noise reduction of chrominance: Vertical shift of the motion detector characteristic [TNRKOC=0]
140
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 17 Bit D7...D4 D3...D0 Name TNRVAY TNRVAC Function Fixed K-factor for temporal noise reduction of luminance [TNRVAY = 15] Fixed K-factor for temporal noise reduction of chrominance [TNRVAC = 15]
Sub address 18 Bit D7 Name TNRSEL Function Motion detection of temporal noise reduction of chrominance: 1: separate motion detector 0: luminance motion detector Temporal noise reduction of luminance: Horizontal shift of the motion detector characteristic [TNRHOY=0] Fixed K-factor switch for temporal noise reduction of luminance: 1: off 0: on
D6...D1
TNRHOY
D0
TNRFIY
Sub address 19 Bit D7 D6...D1 Name x TNRHOC Function x Temporal noise reduction of chrominance: Horizontal shift of the motion detector characteristic [TNRHOC=0] Fixed K-factor switch for temporal noise reduction of chrominance: 1: off 0: on
D0
TNRFIC
141
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 1A Bit D7 Name SNRON Function Spatial noise reduction of luminance: 1: enabled 0: disabled Horizontal panorama mode: 1: on 0: off Gradient of horizontal panorama mode: PANAST+1 [PANAST=7] Temporal Noise Reduction of Luminance and Chrominance On (SRC-Mode) 1: enabled 0: disabled Temporal Noise Reduction of Luminance (SRC-Mode) 1: field based 0: frame based
D6
PANAON
D5...D2 D1
PANAST NRON
D0
DTNRON
Sub address 1B Bit D7...D0 Name OPDELM Function Output processing delay master: Delay(VINM to OPSTARTM) = (OPDELM + 1) * Tline [OPDELM = 170]
Sub address 1C Bit D7...D2 D1...D0 Name
TH_DN_BN
Function Letter Box Detection: Darkness Brightness threshold [TH_DN_BN = 15] Letter Box Detection: Letter Box threshold (MSBs) [TH_LB(5...4) = 0]
TH_LB
142
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 1D Bit D7...D4 D3...D0 Name TH_LB TH_ALB Function Letter Box Detection: Letter Box threshold (LSBs) [TH_LB(3...0) = 12] Letter Box Detection: Amount of letter box threshold [TH_ALB = 6]
Sub address 1E Bit D7 D6...D0 Name x TH_AA Function x Letter Box Detection: Active Area threshold [TH_AA = 50]
Sub address 1F Bit D7...D4 D3...D0 Name
TH_MUNSL
Function Letter Box Detection: Maximum length of insecure threshold [TH_MUNSL = 5]
TH_AUNS Letter Box Detection: Amount of letter box and insecure threshold [TH_AUNS = 7]
Sub address 20 Bit D7...D5 D4...D1 Name x
TH_MA_AA
Function xxx Letter Box Detection: Maximum amount of active area threshold [TH_MA_AA = 14]
143
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 20 Bit D0 Name VOLBD Function Letter Box Detection: Makes the result of letter box detection visible on screen 1: on 0: off
Sub address 22 Bit D7...D5 D4 Name x PLLSOFF Function xxx Only for test purposes, do not use in normal mode PLLS (Clock doubling): 1: off 0: on Only for test purposes, do not use in normal mode PLLS range, only for test purposes [PPLSRA=0]
D3...D0
PLLSRA
Sub address 23 Bit D7...D0 Name IPOSYS Function Vertical Picture Position in the Memory for Slave Picture resolution: 1 line [IPOSYS=0] - upper position
Sub address 24 Bit D7...D0 Name IPOSXS Function Horizontal Picture Position in the Memory for Slave Picture resolution: 4 pixel [IPOSXS=0] - left position
144
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 25 Bit D7...D5 D4...D2 D1...D0 Name Function LEBORDS Amount of left border pixels by horizontal compression slave: 4*LEBORDS [LEBORDS=0] RIBORDS Amount of right border pixels by horizontal compression slave: 4*RIBORDS [RIBORDS=0] CHFILS Chrominance Filter Slave channel on/off 11: vertical and horizontal filter on (only valid for DEZHS=DEZVS=0) 10: horizontal filter on (only valid for DEZHS=0) 01: vertical filter on (only valid for DEZVS=0) 00: off
Sub address 26 Bit D7...D5 Name DELS Function Adjustable delay between luminance and chrominance data slave channel: 111:+4 110:+3 101:+2 100:+1 011: 0 010: -1 001: -2 000: -3
D4
FORCOLS Force colour slave channel 1: on 0: off
YBORDERS
D3...D0
Y border value (Yborder(3) Yborder(2) Yborder(1) Yborder(0) 0 0 0 0 = 00010000 = 16), YBORDERS defines the 4 MSB's of a 8 bit value
145
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 27 Bit D7...D4 Name
UBORDERS
Function U border value (Uborder(3) Uborder(2) Uborder(1) Uborder(0) 0 0 0 0 = 10000000 = 128), UBORDERS defines the 4 MSB's of a 8 bit value V border value (Vborder(3) Vborder(2) Vborder(1) Vborder(0) 0 0 0 0 = 10000000 = 128), VBORDERS defines the 4 MSB's of a 8 bit value
D3...D0
VBORDERS
Sub address 28 Bit D7...D4 D3...D0 Name
UPBORDS
Function Amount of upper border lines by vertical compression master: [UPBORDS=0] Amount of lower border lines by vertical compression master: [LWBORDS=0]
LWBORDS
Sub address 29 Bit D7...D0 Name INTHS Function Interpolation factor for horizontal compression/expansion slave: [INTHS(12...5)=64]
Sub address 2A Bit D7...D3 Name INTHS Function Interpolation factor for horizontal compression/expansion slave: [INTHS(4...0)=0]
146
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 2A Bit D2...D0 Name DEZHS Function Decimation factor for horizontal compression/expansion slave: 111: Factor 16 110: Factor 8 101: Factor 4 100: Factor 2 011: not defined 010: not defined 001: Factor 1 000: Bypass
Sub address 2B Bit D7...D0 Name INTVS Function Interpolation factor for vertical compression slave: INTVS+512 [INTVS(8...1)=0]
Sub address 2C Bit D7 D6...D4 Name INTVS DEZVS Function Interpolation factor for vertical compression slave: INTVS+512 [INTVS(0)=0] Decimation factor for vertical compression slave: 111: Factor 16 110: Factor 8 101: Factor 4 100: Factor 2 011: not defined 010: not defined 001: Factor 1 000: Bypass
147
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 2C Bit D3...D2 Name YPEAKS Function Vertical peaking factor for luminance signal slave: 11: Factor 4 10: Factor 2 01: Factor 1 00: off Vertical peaking factor for chrominance signal slave: 11: Factor 4 10: Factor 2 01: Factor 1 00: off
D1...D0
CPEAKS
Sub address 2D Bit D7 Name
SLAVECON
Function Slave channel connection: 1: Slave channel connected 0: Slave channel not connected Input format slave: 11: full CCIR 656 10: CCIR 656 only data, H- and V-sync according CCIR656 01: CCIR 656 only data, H- and V-sync according PAL/NTSC 00: 4:2:2 Field polarity inversion slave: 1: Field A=1, Field B=0 0: Field A=0, Field B=1 Input filtering of the incoming field signal slave: 1: on 0: off
D6...D5
FORMATS
D4
FIEINVS
D3
VCRMODES
148
Micronas
SDA 9415 - B13
Preliminary Data Sheet
D2...D1
Number of not active pixels from external HINS to the input data (LSBs of in system clocks of CLKS: NAPLIPS) Distance(HINS to input data) = (NAPIPDLS*4+NAPIPPHS+8) [NAPIPPHS = 0]
NAPIPPHS
D0
TWOINS
Chrominance input format slave: 1: 2's complement input (-128...127) 0: unsigned input (0...255) inside the SDA 9415 the data are always processed as unsigned data
Sub address 2E Bit D7...D0 Name
NAPIPDLS
Function
Number of not active pixels from HINS to the input data in (MSBs of system clocks of CLKS: NAPLIPS) Distance(HINS to input data) = (4 * NAPIPDLS + NAPIPPHS + 8) [NAPIPDLS= 0]
Sub address 2F Bit D7...D0 Name ALPFS Function Number of active lines per field after vertical compression slave: Active lines = ALPFS * 2 [ALPFS=144]
Sub address 30 Bit D7...D0 Name APPLS Function Number of active pixels per line in the input data stream after horizontal expansion/compression in system clocks of CLKS: Active pixels = APPLS*8 [APPLS = 180]
149
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 31 Bit D7...D0 Name APPLIPS Function Number of active pixels per line in the input data stream in system clocks of CLKS: Active pixels = APPLIPS*8 [APPLIPS = 180]
Sub address 32 Bit D7...D0 Name ALPFIPS Function Number of active lines per field in the input data stream slave: Active lines = ALPFIPS * 2 [ALPFIPS=144]
Sub address 33 Bit D7...D2 Name VINDELS Function VINS input delay: Delay(VINS to internal V-sync) = (128 * VINDELS + 1)*Tclks [VINDELS = 0] VINS polarity: 1: low active 0: high active HINS polarity: 1: low active 0: high active
D1
VINPOLS
D0
HINPOLS
Sub address 34 Bit D7...D6 Name x Function xx
150
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 34 Bit D7...D1 Name NALIPS Function Number of not active lines per field in the input data stream slave: Not active lines = NALIPS+PD [NALIPS= 20] Enables 16x9 format adjustment for PIP display Chrominance format slave channel: 1: 4:2:0 0: 4:1:1
D0
CHRFORS
Sub address 35 Bit D7...D0 Name Function HOUTDEL Horizontal delay of HOUT and VOUT signal in clocks of CLKD: Delay = 4*HOUTDEL [HOUTDEL = 0]
Sub address 36 Bit D7...D0 Name NALOPD Function Number of not active lines per output frame in the output data stream: Not active lines = 2*(NALOPD+1) [NALOPD = 22]
Sub address 37 Bit D7 D6...D0 Name Function x ALPFOPD Number of active lines per output frame: Active lines = 8 * ALPFOPD [ALPFOPD= 72]
151
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 38 Bit D7...D0 Name LPFOP Function Number of lines per output frame (only valid for VOUTFR=1): Number of lines = 4 * LPFOP + 1 [LPFOP = 156]
Sub address 39 Bit D7...D0 Name NAPOPD Function Number of not active pixels from external HOUT to the first active pixel of the output data stream (when HOUTDEL = 0) in system clocks of X1/CLKD: Distance(HOUT to output data) = (4 * NAPOPD) [NAPOPD = 0]
Sub address 3A Bit D7...D0 Name
HORPOSM
Function Number of pixels from the first active pixel of the main channel to the first active pixel of the master channel in system clocks of X1/CLKD: Number of pixels = (4 * HORPOSM) [HORPOSM = 0]
Sub address 3B Bit D7...D0 Name
HORPOSS
Function Number of pixels from the first active pixel of the main channel to the first active pixel of the slave channel in system clocks of X1/CLKD: Number of pixels = (4 * HORPOSS) [HORPOSS = 0]
152
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 3C Bit D7...D0 Name
VERPOSM
Function Number of lines from the first active line of the main channel to the first active line of the master channel per output frame: Number of lines = VERPOSM [VERPOSM = 0]
Sub address 3D Bit D7...D0 Name Function VERPOSS Number of lines from the first active line of the main channel to the first active line of the slave channel per output frame: Number of lines = VERPOSS [VERPOSS = 0]
Sub address 3E Bit D7 D6...D0 Name x
HORWIDTHM
Function x Number of active pixels per line of the master channel in system clocks of X1/CLKD: Active pixels = 8 * HORWIDTHM [HORWIDTHM = 90]
Sub address 3F Bit D7...D0 Name
HORWIDTHS
Function Number of active pixels per line of the slave channel in system clocks of X1/CLKD: Active pixels = 4 * HORWIDTHS [HORWIDTHS = 180]
153
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 40 Bit D7 D6...D0
VERWIDTHM
Name
Function x Number of active lines per field of the master channel per output frame: Active lines = 8 * VERWIDTHM [VERWIDTHM = 72]
Sub address 41 Bit D7...D0 Name
VERWIDTHS
Function Number of active lines per field of the master channel per output frame: Active lines = 4 * VERWIDTHS [VERWIDTHS = 144]
Sub address 42 Bit D7...D0 Name Function BLANDEL Number of pixels from external HOUT to the active edge of the BLANK signal in system clocks of X1/CLKD: Number of pixels = (8 * (BLANDEL div 4) + BLANDEL mod 3) [BLANDEL = 0]
Sub address 43 Bit D7 D6...D0 Name Function x APPLOPD Number of active pixels per line (including coloured border values and data) in the output data stream in system clocks of X1/CLKD: Active pixels = 8 * APPLOPD [APPLOPD = 90]
154
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 44 Bit D7...D0 Name Function BLANLEN Length of the signal BLANK in system clocks of X1/CLKD: Length = 4 * BLANLEN [BLANLEN = 180]
Sub address 45 Bit D7...D0 Name
PPLOP(7...0)
Function Number of pixels between two output H-syncs HOUT (only valid for HOUTFR=1) in system clocks of X1/CLKD (Bit 7 to 0): Number of pixels = 2 * PPLOP [PPLOP(7...0) = 176]
Sub address 46 Bit D7...D5 D4 Name x Function xxx
PPLOP(8) Number of pixels between two output H-syncs HOUT (only valid for HOUTFR=1) in system clocks of X1/CLKD (Bit 8): Number of pixels = 2 * PPLOP [PPLOP(8) = 1] CAPPM Reduces the active pixels per line of the master channel (HORWIDTHM) at the output side = 8 * HORWIDTHM - 2 * k: k= 24: CAPPM = 11 16: CAPPM = 10 8: CAPPM = 01 0: CAPPM = 00 Reduces the active pixels per line of the slave channel (HORWIDTHS) at the output side = 4 * HORWIDTHS - 2 * k: k= 24: CAPPS = 11 16: CAPPS = 10 8: CAPPS = 01 0: CAPPS = 00
Micronas
D3...D2
D1...D0
CAPPS
155
SDA 9415 - B13
Preliminary Data Sheet
Sub address 47 Bit D7 D6...D0 VERINT Name Function x Vertical expansion factor: 127: no vertical expansion : 85: vertical expansion with factor 1.5 : 63: vertical expansion with factor 2 :
Sub address 48 Bit D7...D5 D4...D1 D0 Name x
STOPMOM
Function xxx Static operation mode for master channel [STOPMOM = 0] Raster mode: 1: progressive 0: interlaced
RMODE
Sub address 49 Bit D7...D4 D3 Name Function INTMODE Free programmable INTERLACED signal for AC coupled deflections [INTMODE = 0]
BLANKPOL
BLANK polarity: 1: low active 0: high active Adaptive operation mode of master channel [ADOPMOM=0]
D2...D0
ADOPMOM
156
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 4A Bit D7 D6 Name x VOUTFR Function x VOUT generator: 1: freerunning-mode 0: locked-mode HOUT generator 1: freerunning-mode 0: locked-mode
D5
HOUTFR
D4
VOUTPOL VOUT polarity: 1: low active 0: high active HOUTPOL HOUT polarity: 1: low active 0: high active
STOPMOS
D3
D2...D0
Static operation mode for slave channel [STOPMOS = 0]
Sub address 4B Bit D7 Name Function PRIORMS Priority of master or slave channel: 1: Master channel priority 0: Slave channel priority FILSEL Filter select for VDU interpolation 11: Improved median based interfield interpolation (SRC) 10: median based interfield interpolation 01: linear INTRAFIELD interpolation (SSC and MUP mode) 00: linear INTERFIELD interpolation Inversion of internal MOVPH signal 1: enabled 0: disabled Vector smoothing 1: on 0: off
Micronas
D6...D5
D4
MOVPHINV
D3
MESMOOTHON
157
SDA 9415 - B13
Preliminary Data Sheet
Sub address 4B Bit D2 Name
MENULLUNFON
Function Unfiltered null DBD 1: on 0: off Minimum vector threshold for film mode and global motion detection 11: 3 10: 2 01: 1 00 :0
D1...D0
MEMINMOT
Sub address 4C Bit D7...D4 Name
MEPENUP
Function Penalty for update vectors 1111: 15 1110: 14 : 1000: 8 : 0001: 1 0000: 0 Additional penalty for non-null vectors 1111: 15 1110: 14 : 1000: 8 : 0001: 1 0000: 0
D3...D0
MEADDPEN
158
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 4D Bit D7...D6 Name Function SFMAXTH Scale factor for MEMAXTH 11: *64 10: *32 01: *16 00: *8 SFMINTH Scale factor for MEMINTH 11: *64 10: *32 01: *16 00: *8
D5...D4
D3...D0
MEMINTH Threshold for detection of motion in camera mode 1111 : 15 1110 : 14 : 0111 : 7 : 0001: 1 0000: 0
Sub address 4E Bit D7...D6 D5 Name xx BVMCON Function xx Vector correction 1: on 0: off Threshold for detection of motion in film mode 11111 : 31 11110 : 30 : 00001: 1 00000: 0
D4...D0
MEMAXTH
159
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 4F Bit D7...D4 Name
MEMOHIST
Function History length of film mode and global motion detection 1111 : 15 1110 : 14 : 0011: 3 : 0001: 1 0000: 0 Additional penalty for null vector, if vector length of predictor is greater as MENPTH 1111: 15 1110: 14 : 1000: 8 : 0001: 1 0000: 0
D3...D0
MENULLPEN
Sub address 50 Bit D7...D6 Name MEANBP Function Penalty for border lines in additional null dbd 11: *4 10: *2 01: *1 00: *0 Penalty for middle lines in additional null dbd 11: *8 10: *4 01: *2 00: *1
D5...D4
MEANMP
160
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 50 Bit D3..D1 Name MENPTH Function Minimum vector length for null dbd penalty 111: off 110: 24 101: 20 100: 16 011: 12 010: 8 001: 4 000: 0 Influence of periodicity on 1: update vector length 0: update vector penalty
D0
MEPERINF
Sub address 51 Bit D7...D6 Name
MEANRG
Function Range of middle lines in additional null dbd 11: 10 lines 10: 8 lines 01: 6 lines 00: 4 lines Threshold for horizontal periodicity detection 111: 112 110: 96 101: 80 100: 64 011: 48 010: 32 001: 16 000: off
D5...D3
MEHPERTH
161
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 51 Bit D2...D0 Name
MEVPERTH
Function Threshold for vertical periodicity detection 111: 112 110: 96 101: 80 100: 64 011: 48 010: 32 001: 16 000: off
Sub address 52 Bit D7 D6 Name x BVMRES Function x Block vector memory reset 1: All vector memory output values are set to null vector (for scan rate conversion and vector estimation). Corrupt vectors are avoided, suppressed or deleted. This is equal to a reset of the vector memory. 0: Use vectors stored in vector memory Penalty for periodic structures. Reduces estimation errors inside horizontal periodic structures. 111: off 110: strong : 011: recommended : 000: slight
D5...D3
PERPEN
162
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 52 Bit D2 Name
VECDISON
Function Display of vector estimation results in chrominance channel 1: on 0: off If VECDISON is on, the IC Bus parameter FILSEL can be used to choose between different display modi: FILSEL: 11: x-vector: v-component; y-vector: u-component 10: x-vector: u-component; y-vector: v-component 01: y-vector: u- and v-component 00: x-vector: u- and v-component Time hysteresis for film mode detection on/off: 1: on (camera->film: 2*(MEMOHIST+1); film->camera: (MEMOHIST+1) 0: off (2*(MEMOHIST+1)) Reset of film detection time hysteresis queue 1: Reset: MOVMO=0 (camera mode) 0: no reset
D1
THYON
D0
RESMOV
Sub address 53 Bit D7...D6 Name Function REFRPER Refresh Period of the Memory (REFRON=1; 50 Hz, 625 lines standard) 11: ~4 ms 10: ~5.5 ms 01: ~7 ms 00: ~10 ms MEMOP Memory Operation Mode 11:not defined 10:MUP-Mode (Multi-Picture) 01:SSC-Mode (Split Screen) 00:SRC-Mode (Sample Rate Conversion) Reading Data of Master Channel 1: enabled (master picture is displayed) 0: disabled
D5...D4
D3
MASTERON
163
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 53 Bit D2 Name Function SLAVEON Reading Data of Slave Channel 1: enabled (slave picture is displayed) 0: disabled MEMRDM Memory Read Mode Master Channel (SRC-Mode) 1:reading only 1 field memory area for AABB conversion 0:reading both field memory areas for ABAB conversion MEMRDS Memory Read Mode Slave Channel (SRC-Mode) 1:reading data in SSC-configuration, 1 or 2 decimated fields, AABB 0:reading data in PIP-configuration (joint line free, ABAB)
D1
D0
Sub address 54 Bit D7...D0 Name VPAN Function Vertical Panning -line number indicating the start line of reading for the master channel -defines the displayed part of the picture with activated vertical interpolation [VPAN=0]
Sub address 55 Bit D7 Name REFRON Function Refresh On 1: memory refresh activated 0: no memory refresh Joint Line Free Display of Master Channel by Shifting the Output Raster Phase (SSC-Mode): Should be set in all operation modes to 1 1: enabled 0: disabled
D6
RSHFTM
164
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 55 Bit D5 Name RSHFTS Function Joint Line Free Display of Master and Slave Channel by Shifting the Output Raster Phase (SSC-Mode, RSHFTM=1): Should be set in all operation modes to 1 1: enabled 0: disabled Increment for Raster Phase Shift per Output Frame (lines) [SHFTSTEP=0100]
D4...D1 D0
SHFTSTEP
MASTSLA Master / Slave Switch 1: master and slave input signals are exchanged, reset of display raster shift 0: display raster is synchronized to input Master Channel (vertical Sync)
Sub address 56 Bit D7...D1 D0 Name
PROG_ THRES MASLSHFT
Function Threshold to display progressive PIP without joint lines [PROG_THRES=60] Master / Slave Shift 1: display raster is shifted slave phase to prepare a master/ slave switch 0: display raster is synchronized to input Master Channel (vertical Sync)
Sub address 57 Bit D7...D5 Name xxx Function xxx
165
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 57 Bit D4 Name Function MEMWRS Memory Write Mode Slave Channel (SRC-Mode) - SRC-Mode: 1:writing data in PIP-configuration and additionally in SSCconfiguration 0:writing data in PIP-configuration - SSC- and MUP-Mode: 1:768 pixel/line 0:512 pixel/line D3 FREEZES Freeze Picture Slave 1: freezed (no writing of slave data) 0: live WRFLDS Write Field Slave Channel (only MUP Mode) 1: only A fields are written 0: all fields are written corresponding on actual mode Data Configuration of the Memory (Slave Channel) 0:slave channel blocked (SRC-Mode, ORGMEMM=1) 1 field (SSC- and MUP-Mode; SRC-Mode, ORGMEMM=0) 1:3 fields PIP (SRC), 2 fields (restricted picture size, SSC and MUP)
D2
D1
ORGMEMS
D0
VERRESS Vertical Resolution Slave Channel (only MUP Mode) (ORGMEMS=1 and WRFLDS=1) 1: frame resolution 0: field resolution
Sub address 58 Bit D7...D5 D4 Name xxx Function xxx
MEMWRM Memory Write Mode Master Channel - SRC-Mode: no meaning, should be set to '0' - SSC- and MUP-Mode: 0:512 pixel/line 1:768 pixel/line
166
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 58 Bit D3 Name Function FREEZEM Freeze Picture Master 1: freezed (no writing of master data) 0: live WRFLDM Write Field Master Channel (only MUP Mode) 1: only A fields are written 0: all fields are written corresponding on actual mode Data Configuration of the Memory (Master Channel) 1:2 fields (restricted picture size in SSC- and MUP-Mode) 0:1 field Vertical Resolution Master Channel (MUP Mode) (ORGMEMM=1 and WRFLDM=1) 1: frame resolution 0: field resolution
D2
D1
ORGMEMM
D0
VERRESM
Sub address 59 Bit D7...D4 Name
MEMMNDTH
Function Threshold for switching between the vector activity or the field difference as input for the film mode detection Use field difference as film mode detection input 1111: insensible to motion : 0001: sensible to motion 0000: use vector activity as film mode detection input Null vector reliability threshold, makes detection of null vector in homegenous areas more reliable. Threshold value to adjust sensibility of null vector reliability: 1111: insensible : 0001: sensible to motion and noise 0000: off
D3...D0
MENVRTH
167
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 5A Bit D7 D6 Name DOUTEN TWOOUT Function
1: Digital output enabled 0: Digital output disabled
Chrominance output format: 1: 2's complement output (-128...127) 0: unsigned output (0...255) inside the SDA 9415 the data are always processed as unsigned data, used in DP, makes only sense for digital output Only for test purposes, do not use in normal mode 1: DAC enabled 0: DAC disabled 1: coring on 0: coring off Y border value of display (Yborderd(3) Yborderd(2) Yborderd(1) Yborderd(0) 0 0 0 0 = 00010000 = 16), YBORDERD defines the 4 MSB's of a 8 bit value
D5
DACEN
D4 D3...D0
CORING
YBORDERD
Sub address 5B Bit D7...D4 Name
UBORDERD
Function U border value of display (Uborderd(3) Uborderd(2) Uborderd(1) Uborderd(0) 0 0 0 0 = 10000000 = 128), UBORDERD defines the 4 MSB's of a 8 bit value V border value of display (Vborderd(3) Vborderd(2) Vborderd(1) Vborderd(0) 0 0 0 0 = 10000000 = 128), VBORDERD defines the 4 MSB's of a 8 bit value
D3...D0
VBORDERD
168
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 5C Bit D7...D6 Name
ASCENTLTI
Function Defines slope of DLTI gain function 00: 1/2 01: 1 10: 2 11: 4 Defines slope of DCTI gain function 00: 1/2 01: 1 10: 2 11: 4 Delay of the luminance signal in relation to the chrominance signal in 2*CLKD clocks: 1111: +7 1110: +6 : 1000: +0 : 0001: -7 0000: -8
D5...D4
ASCENTCTI
D3...D0
COARSDEL
169
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 5D Bit D7...D4 Name BCOF Function Defines the band pass filter adjustments 0000: 0 0001: 1/4 : . 0100: 1 : : . 1100 12/4 1101 14/4 1110 16/4 1111 20/4 Defines the high pass filter adjustments 0000: 0 0001: 1/4 : . 0100: 1 : : . 1100 12/4 1101 14/4 1110 16/4 1111 20/4
D3...D0
HCOF
Sub address 5E Bit D7 Name CHROM_ AMP Function Chrominance amplification factor adjustment for DAC output 1: amplification factor 2 0: amplification factor 1
170
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 5E Bit D6...D5 Name
THRESY_UP
Function Defines the upper threshold for luminance 00: 255 (no upper threshold) 01: 32 10: 128 11: 64 Defines the threshold for chrominance 00: 255 (DCTI OFF) 01: 4 10: 8 11: 12 defines the threshold for luminance 000: 255 (DLTI OFF) 001: 4 010: 8 011: 12 100: 16 : 111: 28
D4...D3
THRESC
D2...D0
THRESY
Sub address 5F Bit D7 D6 Name x
CLKMDEN
Function x CLKMDEN 1: X1/CLKD 0: CLKM CLKOUTON 1: enabled 0: disabled Only for test purposes, do not use in normal mode PLLM (Clock doubling): 1: off 0: on Only for test purposes, do not use in normal mode PLLM range, only for test purposes [PPLDRA=0]
Micronas
D5
CLKOUTON
D4
PLLDOFF
D3...D0
PLLDRA
171
SDA 9415 - B13
Preliminary Data Sheet
Sub address 78 Bit D7...D0 Name SLAA Function Letter box detection: First Line of Active Area = 2 * SLAA
Sub address 79 Bit D7...D0 Name ELAA Function Letter box detection: End Line of Active Area = 2 * ELAA
Sub address 7A Bit D7...D3 D2...D0 Name Function NOISEME Noise level of the input signal: 0 (no noise), ..., 30 (strong noise) [31 (strong noise or measurement failed)] VERSION Version of SDA 94XX family: 000: SDA 9400 001: SDA 9401 010: SDA 9402 100: SDA 9410
Sub address 7B Bit D7...D4 D3 Name xxxx
Status_SLAA
Function xxxx Letter box detection: Status of SLAA 1: SLAA is reliable 0: SLAA is not reliable Letter box detection: Status of ELAA 1: ELAA is reliable 0: ELAA is not reliable
Micronas
D2
Status_ELAA
172
SDA 9415 - B13
Preliminary Data Sheet
Sub address 7B Bit D1 Name RELY Function Letter box detection: Reliability signal 1: All values determined by the Letter Box detection algorithm are reliable 0: One or more values determined by the Letter Box detection are not reliable TV mode of the input signal master 1: NTSC 0: PAL
D0
TVMODEM
Sub address 7C Bit D7...D2 D1 Name xxxxxx
NMSTATUS
Function xxxxxx Status bit for noise measurement IC Bus parameter 1: New value of NOISEME available 0: NOISEME has not been updated Status bit for letter box detection IC Bus parameter 1: New values of Letter Box Detection algorithm available 0: Values of Letter Box Detection has not been updated
D0
LBDSTATUS
Sub address 7D Bit D7...D1 D0 Name xxxxxxx
TVMODES
Function xxxxxxx TV mode of the input signal slave 1: NTSC 0: PAL
173
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Sub address 7E Bit D7 Name MOVMO Function Film mode 1: film mode 0: camera mode Film mode phase 1 - An+1 and Bn has the same phase 0 - An and Bn has the same phase
D6
MOVPH
D5
GMOTION Global motion detection 1: if no STILL scene is detected (minimum is: 1 field in motion of 32 fields in order) 0: if STILL scene is detected (32 fields in order without motion) MOVTYP Film mode type 1: NTSC film mode source with 24 motion phases per second (2-3 pull down) 0: PAL film mode source with 25 motion phases per second Statistics about motion blocks
D4
D3...0
MEMSTAT
Sub address 7F Bit D7...D1 D0 Name xxxxxxx
SHIFTACT
Function xxxxxxx Shifting of Display Raster Phase Active 1: phase shift in progress 0: phase shift not active
Sub address 80 Bit D7...D1 Name xxxxxxx Function xxxxxxx
174
Micronas
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Preliminary Data Sheet
Sub address 80 Bit D0 Name
VIMSTATUS
Function Status bit for sub addresses, which will be made valid by VINM 0: New write or read cycle can start 1: No new write or read cycle can start
Sub address 81 Bit D7...D1 D0 Name xxxxxxx
VISSTATUS
Function xxxxxxx Status bit for sub addresses, which will be made valid by VINS 0: New write or read cycle can start 1: No new write or read cycle can start
Sub address 82 Bit D7...D1 D0 Name xxxxxxx
OSSTATUS
Function xxxxxxx Status bit for sub addresses, which will be made valid by OPSTARTM 0: New write or read cycle can start 1: No new write or read cycle can start
175
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Electrical Characteristics
6
6.1
Electrical Characteristics
Absolute maximum ratings
Parameter Operating Temperature Storage Temperature Junction Temperature Soldering Temperature Soldering Time Input Voltage Output Voltage Input Voltage Output Voltage Supply Voltages Supply voltage differentials
Symbol TA Tstg TJ TS tS VI VQ VI VO VDD VDD
Min 0 -65
Max 70 125 125 260 10
Unit C C C C s V V V V V V
Remark
-0.3 -0.3 -0.3 -0.3 -0.3 -0.25
VDD+0.3 VDD+0.3 5.5 5.5 3.8 0.25
not valid for IC Bus pins not valid for IC Bus pins IC Bus pins only IC Bus pins only
between any internally non-connected supply pins of the same kind, see Pin Configuration for any single output for any single output for any single output
DAC output current DAC output voltage RREF_I output current Total Power Dissipation ESD Protection ESD Protection
IO
-30 -0.3 VDD+0.3
mA mA mA 1.8 W kV kV
IO THD ESD ESD
-5
-2,0 -1,5
2,0 1,5
MIL STD 883C method 3015.6, 100pF, 1500=_ EOS/ESD Assn. Standard DS 5.3-1993 (CDM)
Latch-Up Protection
-100
100
mA
all inputs/outputs
All voltages listed are referenced to ground (0V, VSS) except where noted. Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions or at any other condition beyond those indicated in the operational sections of this specification is not implied.
176
Micronas
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Preliminary Data Sheet
Electrical Characteristics
6.2
Parameter
Operating range
Symbol VDD TA Min 3.15 0 Nom 3.3 25 Max 3.45 70 Unit V C Remark
Supply Voltages Ambient Temperature All TTL Inputs High-Level Input Voltage Low-Level Input Voltage Input Current All TTL Outputs High-Level Output Voltage Low-Level Output Voltage INPUT/OUTPUT: SDA Low-Level Output Voltage Clock TTL Input CLKM Clock frequency
VIH VIL IIN
2.0V -0.2
VDD +0.2 0.8
V V
+/- 5 A
VOH VOL
2.4 0.4
V V
IOH = -2.0 mA IOL = 2.0 mA
VOL
0.5
V
at IOL = max
1/T
27
MHz
see "Timing diagram clock" on page 183
Low time High time Rise time Fall time Input SYNCENM Low time
tWL tWH tTLH tTHL
10 10 10 10
ns ns ns ns
tWL
22
ns
see "Timing diagram clock" on page 183
High time Rise time Fall time Clock TTL Input CLKS Clock frequency
tWH tTLH tTHL
22 10 10
ns ns ns
1/T
27
MHz
see "Timing diagram clock" on page 183
Low time High time Rise time Fall time
tWL tWH tTLH tTHL
10 10 10 10
ns ns ns ns
177
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Electrical Characteristics
Parameter Input SYNCENS Low time tWL 22 ns see "Timing diagram clock" on page 183 Symbol Min Nom Max Unit Remark
High time Rise time Fall time Clock TTL Input X1/CLKD Clock frequency
tWH tTLH tTHL
22 10 10
ns ns ns
1/T
27
MHz
see "Timing diagram clock" on page 183
Low time High time Rise time Fall time
tWL tWH tTLH tTHL
10 10 5 5
ns ns ns ns
IC Bus (All Values Are Referred To min(VIH) And max(VIL)), fSCL = 400 KHz High-Level Input Voltage VIH 3 5.25 V see "IC Bus timing START/STOP" on page 182 see "IC Bus timing DATA" on page 182
Low-Level Input Voltage
VIL
0
1.5
V
SCL Clock Frequency Inactive Time Before Start Of Transmission Set-Up Time Start Condition Hold Time Start Condition SCL Low Time SCL High Time Set-Up Time DATA Hold Time DATA SDA/SCL Rise Times SDA/SCL Fall Times Set-Up Time Stop Condition Output valid from clock Input filter spike suppression (SDA and SCL pins) Low-Level Output Current
fSCL tBUF tSU;STA tHD;STA tLOW tHIGH tSU;DAT tHD;DAT tR tF tSU;STO tAA tSP IOL
0 1.3 0.6 0.6 1.3 0.6 100 0
400
kHz s s s s s ns s
300 300 0.6 900 50 3
ns ns s ns ns mA
178
Micronas
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Preliminary Data Sheet
Electrical Characteristics
Parameter Inputs crystal connections X1/CLKD, X2 Symbol Min Nom Max Unit Remark see "Clock circuit diagram" on page 183 Xtal Cin Cout ZR 40 27.0 27 27 MHz pF pF fundamental crystal
Crystal frequency Equivalent parallel Capacitance Equivalent parallel Capacitance Resonance impedance Digital-To-Analog-Conversion DAC sample rate RREF_I output current UREF_I input voltage
fs Iref Uref
4.5 -1.3 0.8
54.0 -1.9 0.9
60 -2.5 1.0
MHz mA V
6.3
Parameter
Characteristics (Under operating range conditions)
Symbol Min t.b.d. Max Unit Remark All VDD pins, typ. t.b.d.mA
Average Supply Current All Digital Inputs (Including I/O Inputs) Input Capacitance Input Leakage Current
t.b.d. mA
10 -5 5
pF A
TTL Inputs: YINM, UVINM, HINM, VINM (Referenced To CLKM) Set-Up Time Input Hold Time tSU tIH 7 6 ns ns see "Timing diagram clock" on page 183
TTL Inputs: YINS, UVINS, HINS, VINS (Referenced To CLKS) Set-Up Time Input Hold Time tSU tIH 7 6 ns ns see "Timing diagram clock" on page 183
TTL Outputs: HOUT, VOUT, BLANK (Referenced To CLKOUT) Hold time Delay time tOH tOD 6 25 ns ns see "Timing diagram clock" on page 183 CL = 50 pF, 27 MHz
TTL Inputs: SYNCENM (Referenced To CLKM) Set-Up Time Input Hold Time tSU tIH 25 0 ns ns see "Timing diagram clock" on page 183
TTL Inputs: SYNCENS (Referenced To CLKS) Set-Up Time tSU 25 ns see "Timing diagram clock" on page 183
179
Micronas
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Preliminary Data Sheet
Electrical Characteristics
Input Hold Time tIH 0 ns
Digital-To-Analog Conversion (9 bit): Current Source Outputs IY_O, IU_O, IV_O Full range output current Full range output matching Full range output accuracy Current source output resistance Supply voltage dependency of IOFR Temperature dependency of IOFR Full range output voltage DC differential non-linearity DC differential integral non-linearity IOFR -19 -17 3% 3% k 0.01 5 10 1.5 -1 -2 1 2 mA/ V A/ C V LSB LSB mA Uref=typ., TA=nom., IREF=typ., RL=75 DAC output U and V to each other within operating range Uref=nom., TA=nom., IREF=nom. Uref=nom., TA=nom., IREF=nom., RL=75 Uref=nom., IREF=nom., RL=75 Uref=nom., TA=nom., IREF=nom.
DDLOUT -3% DLOUT RO dI/dVDD dIOFR VO DNL INL -3% 20 0.015 -10
DAC Reference Pins: UREF_I, RREF_I (analog) Offset voltage between UREF_I and RREF_I UREF_I input current UOFFSET IUREF -40 -10 40 10 mV A
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Micronas
SDA 9415 - B13
Preliminary Data Sheet
Application information
7
Application information
YUV/ ITU 601 CVBS Y/C RGB VPC32xxD Color Decoder R CLKM = 27 MHz SDA 9415 DAEDALUS DDP3310B or SDA 9380 Deflection controller G B
8
YUV
E/W V-Drive H-Drive
YUV/ ITU 601 CVBS Y/C RGB VPC32xxD Color Decoder CLKS = 27 MHz
8
Figure 55
Application for SDA 9415
181
Micronas
SDA 9415 - B13
Preliminary Data Sheet
Wave forms
8
8.1
Wave forms
IC Bus timing START/STOP
8.2
IC Bus timing DATA
tf tR t LOW
BUS TIMING DATA
t HIGH
SCL t SU;STA SDA IN t SP tAA SDA OUT tAA tHD;STA t HD;STA t SU;DAT
t SU;STO
i2ctimdat
t BUF
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Micronas
i2ctimd01
SDA 9415 - B13
Preliminary Data Sheet
Wave forms
8.3
Timing diagram clock
T CLKM/S CLKOUT tWH tHL tWL VIH VIL tSU2 SYNCENM/S tWH2 tIH2
Datain Datain
tLH tWL2
tHL2
tLH2
tIH
Dataout
tOD
tSU
Dataout
tOH
8.4
Clock circuit diagram
X1/CLK2
X2
xtal
quartz
Cin
Cout
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Micronas
SDA 9415 - B13
Preliminary Data Sheet
Package Outlines
9
Package Outlines
P-MQFP-144-2
[all dimensions in mm]
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Micronas
SDA 9415-B13
PRELIMINARY DATA SHEET
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-560-1PD
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
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Micronas

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